CN-121983107-A - Flash memory test method, electronic device and storage medium

Abstract

The embodiment of the application provides a flash memory test method, electronic equipment and a storage medium, wherein the method comprises the steps of determining an abnormal power supply scene and an abnormal operation command; and responding to the end of the abnormal power supply scene, and carrying out data detection on the flash memory to be tested to obtain a test result of the flash memory to be tested. The embodiment of the application can test the influence of the synergistic effect between the abnormal command and the power failure on the flash memory, thereby improving the reliability of the flash memory test.

Inventors

• LONG CHANG
• SU JIEWEI
• LAI NAI

Assignees

• 珠海妙存科技有限公司

Dates

Publication Date

20260505

Application Date

20251210

Claims (10)

1. 1. A method for testing flash memory, comprising: determining an abnormal power supply scene and an abnormal operation command; Responding to power supply of the flash memory to be tested according to the abnormal power supply scene, and operating the flash memory to be tested according to the abnormal operation command; and responding to the end of the abnormal power supply scene, and carrying out data detection on the flash memory to be tested to obtain a test result of the flash memory to be tested.
2. 2. The method of claim 1, wherein the performing data detection on the flash memory to be tested to obtain a test result of the flash memory to be tested comprises: Initializing the flash memory to be tested to obtain abnormal operation state information of the flash memory to be tested; data comparison is carried out on the data of the flash memory to be tested, and data abnormal state information of the flash memory to be tested is obtained; And determining the test result according to the abnormal operation state information and the abnormal data state information.
3. 3. The method of claim 2, wherein operating the flash memory under test according to the abnormal operation command comprises: responding to the abnormal operation command including a writing command, and determining a data block to be tested in the flash memory to be tested according to the writing command; erasing the data block to be tested in response to the fact that the data block to be tested is legal; And writing the preset data to be written into the erased data block to be tested.
4. 4. The method of claim 3, wherein the comparing the data of the flash memory to be tested to obtain the data abnormal state information of the flash memory to be tested comprises: Responding to the abnormal power supply scene including a power-down scene, and determining a corresponding target write page in the flash memory to be tested at the power-down moment; Determining first target data corresponding to a data page before the target write page in the data to be written in the data block to be tested; And comparing the first target data with all data before the target writing page in the flash memory to be tested to obtain the data abnormal state information.
5. 5. The method of claim 4, wherein comparing the first target data with all data prior to the target write page in the flash memory under test to obtain the data exception status information comprises: determining second target data corresponding to the target writing page in the data to be written in the data block to be tested in response to the first target data being the same as all data before the target writing page in the flash memory to be tested; And verifying according to the second target data to obtain the data abnormal state information.
6. 6. A method according to claim 3, characterized in that the method further comprises: responding to the writing command, updating the writing process of the erased data block to be tested, stopping the writing of the data to be written to the data block to be tested, and determining a new data block to be tested according to the updated writing command; Erasing the new data block to be tested in response to the new data block to be tested being legal; And writing the preset new data to be written into the erased new data block to be tested.
7. 7. The method of claim 6, wherein the comparing the data of the flash memory to be tested to obtain the data abnormal state information of the flash memory to be tested comprises: responding to the abnormal power supply scene as a power-down scene, and generating power down before and after the update of the write command, determining a first target write page corresponding to the power-down moment before the update of the write command in the data block to be tested, and a second target write page corresponding to the power-down moment after the update of the write command in the new data block to be tested; Determining third target data corresponding to a data page before the first target writing page in the data to be written in the data block to be tested, and fourth target data corresponding to a data page before the second target writing page in the new data to be written in the new data block to be tested; Comparing the third target data with all data before the first target writing page in the data block to be tested, and comparing the fourth target data with all data before the second target writing page in the new data block to be tested, so as to determine the data abnormal state information.
8. 8. The method of claim 7, wherein comparing the third target data with all data prior to the first target write page in the block of data under test and comparing the fourth target data with all data prior to the second target write page in the new block of data under test to determine the data exception status information comprises: Determining fifth target data corresponding to the first target writing page in the data to be written in the data to be tested block according to the fact that the third target data is the same as all data before the first target writing page in the data to be tested; verifying according to the fifth target data to obtain a first verification result; Determining, in the new data block to be tested, sixth target data corresponding to the second target write page in the new data block to be tested, in response to the fourth target data being the same as all data preceding the second target write page in the new data block to be tested; Verifying according to the sixth target data to obtain a second verification result; And obtaining the data abnormal state information according to the first verification result and the second verification result.
9. 9. An electronic device, comprising: At least one processor; At least one memory for storing at least one program; A flash memory testing method according to any one of claims 1 to 8, when at least one of said programs is executed by at least one of said processors.
10. 10. A computer readable storage medium storing computer executable instructions for performing the flash memory testing method according to any one of claims 1 to 8.

Description

Flash memory test method, electronic device and storage medium Technical Field Embodiments of the present application relate to, but are not limited to, the field of storage technologies, and in particular, to a flash memory testing method, an electronic device, and a storage medium. Background In the related art, with the continuous improvement of the storage density and the manufacturing process of the flash memory, the reliability problem of the flash memory under the abnormal power supply working condition is increasingly outstanding. In practical application, the flash memory not only encounters abnormal power supply working conditions such as sudden power failure, power supply jitter and the like, but also has the key that the power supply anomalies often generate synergistic effects with abnormal commands (such as illegal operation instructions, out-of-range address access and the like) which are executed by the equipment, so that a composite fault mode is formed. The current flash memory test mode is to identify the working state by monitoring the R/B pin of the flash memory, trigger the power-off operation of the controllable power supply when the busy state is detected, and finally evaluate the power-off threshold voltage distribution diagram, however, the test mode can only simulate a single power abnormal scene, cannot test the influence of the synergistic effect between the abnormal command and the power failure on the flash memory, and cannot evaluate the reliability of the flash memory completely. Disclosure of Invention The embodiment of the application provides a flash memory testing method, electronic equipment and a storage medium, which can test the influence of the synergistic effect between an abnormal command and a power failure on a flash memory, thereby improving the reliability of flash memory testing. In one aspect, an embodiment of the present application provides a flash memory testing method, including: determining an abnormal power supply scene and an abnormal operation command; Responding to power supply of the flash memory to be tested according to the abnormal power supply scene, and operating the flash memory to be tested according to the abnormal operation command; and responding to the end of the abnormal power supply scene, and carrying out data detection on the flash memory to be tested to obtain a test result of the flash memory to be tested. In an embodiment, the performing data detection on the flash memory to be tested to obtain a test result of the flash memory to be tested includes: Initializing the flash memory to be tested to obtain abnormal operation state information of the flash memory to be tested; data comparison is carried out on the data of the flash memory to be tested, and data abnormal state information of the flash memory to be tested is obtained; And determining the test result according to the abnormal operation state information and the abnormal data state information. In an embodiment, the operating the flash memory to be tested according to the abnormal operation command includes: responding to the abnormal operation command including a writing command, and determining a data block to be tested in the flash memory to be tested according to the writing command; erasing the data block to be tested in response to the fact that the data block to be tested is legal; And writing the preset data to be written into the erased data block to be tested. In an embodiment, the comparing the data of the flash memory to be tested to obtain the data abnormal state information of the flash memory to be tested includes: Responding to the abnormal power supply scene including a power-down scene, and determining a corresponding target write page in the flash memory to be tested at the power-down moment; Determining first target data corresponding to a data page before the target write page in the data to be written in the data block to be tested; And comparing the first target data with all data before the target writing page in the flash memory to be tested to obtain the data abnormal state information. In an embodiment, the comparing the first target data with all data before the target writing page in the flash memory to be tested to obtain the data abnormal state information includes: determining second target data corresponding to the target writing page in the data to be written in the data block to be tested in response to the first target data being the same as all data before the target writing page in the flash memory to be tested; And verifying according to the second target data to obtain the data abnormal state information. In an embodiment, the method further comprises: responding to the writing command, updating the writing process of the erased data block to be tested, stopping the writing of the data to be written to the data block to be tested, and determining a new data block to be tested according to the updated writing command; Erasing the new