CN-121983786-A - Ultralow noise tile type phased array surface based on silicon-based chip

Abstract

The embodiment of the disclosure provides an ultralow noise tile type phased array surface based on a silicon-based chip, which comprises an antenna part PCB board, wherein the antenna part PCB board comprises an array antenna, an LNA chip, a board-level filter, a BFIC chip based on a silicon-based process and a power division network which are sequentially connected, the array antenna is provided with a patch antenna, a feed point of the patch antenna is directly connected with the LNA chip through a metallized hole, the LNA chip is connected with the board-level filter through the metallized hole, the board-level filter is connected with the BFIC chip through the metallized hole, the BFIC chip is connected with the power division network through the metallized hole, and the LNA chip is integrated with a dynamic tuning matching circuit which can perform dynamic impedance matching according to the working condition of the patch antenna. In this way, the tile-type phased array surface provided by the embodiment of the disclosure realizes the compromise of high integration, low noise, low loss, dynamic matching and anti-interference, and overcomes the defects of the traditional tile-type phased array surface in the aspects of integration, noise, loss, matching flexibility, filtering and the like.

Inventors

• WANG BO
• WANG GEYANG
• SU MINGYANG
• LIU ZHIZHE
• CAO YUXIONG
• CHEN KUNYUN
• CHEN LINHUI
• Duan Youyou
• LIU YICHAO
• QIN HAN

Assignees

• 航天科工拓维电子科技(上海)有限公司

Dates

Publication Date

20260505

Application Date

20251230

Claims (10)

1. 1. The ultra-low noise tile-type phased array surface based on the silicon-based chip is characterized by comprising an antenna part PCB board, wherein the antenna part PCB board comprises an array antenna, an LNA chip, a board-level filter, a BFIC chip and a power division network which are sequentially connected, the array antenna is provided with a patch antenna, a feed point of the patch antenna is directly connected with the LNA chip through a metalized hole, the LNA chip is connected with the board-level filter through the metalized hole, the board-level filter is connected with the BFIC chip through the metalized hole, the BFIC chip is connected with the power division network through the metalized hole, and the LNA chip is integrated with a dynamic tuning matching circuit which can perform dynamic impedance matching according to the working condition of the patch antenna.
2. 2. The tile phased array of claim 1, wherein the BFIC chips and the LNA chips are disposed on a top layer of the antenna portion PCB, the power splitting network is disposed on a second layer of the antenna portion PCB, the board-level filter is disposed on a third layer of the antenna portion PCB, and the array antenna is disposed on a bottom layer of the antenna portion PCB.
3. 3. The tile phased array surface of claim 2, wherein the board-level filter is deployed in a stripline form on a third layer of the antenna portion PCB board.
4. 4. The tile phased array surface of claim 3, wherein the metallized hole comprises a coaxial-like through hole and a blind hole, wherein a feed point of the patch antenna is directly connected with the LNA chip through the coaxial-like through hole, the LNA chip is connected with a board-level filter through the blind hole, the board-level filter is connected with the BFIC chip through the blind hole, and the BFIC chip is connected with a power division network through the blind hole.
5. 5. The tile phased array surface of claim 4, wherein one BFIC chip is placed in the center of each 4 patch antennas, 4 LNA chips are surrounded around each BFIC chip, and the input end of each LNA chip coincides with two feed points of the corresponding patch antenna and is directly connected through a coaxial-like through hole.
6. 6. The phased array surface of claim 5, wherein a spacing between patch antennas is determined by an operating frequency of the phased array surface.
7. 7. The phased array tile surface of claim 6, further comprising a non-antenna portion PCB board, wherein the non-antenna portion PCB board comprises a power module, a control module, and an external interface; The power supply module is used for supplying power to the tile type phased array surface; The control module is used for controlling the tile type phased array surface; the external interface is used for external communication.
8. 8. The tile-type phased array surface of claim 7, wherein the BFIC chips are 8-channel BFIC chips, when the tile-type phased array surface works, radio frequency links corresponding to each channel receive radio frequency signals through the patch antennas, the radio frequency signals enter the LNA chip through quasi-coaxial through holes to be amplified in low noise, the amplified radio frequency signals enter the board-level filter through blind holes to be filtered by interference signals, the filtered radio frequency signals enter the BFIC chip through blind holes to be formed into beams, the BFIC chips output beams corresponding to the 8 channels to the power division network in one path, the power division network synthesizes the received beams output by each BFIC chip in one path, and then outputs directional reception beams to the outside through the external interface.
9. 9. The phased array of claim 8, wherein the patch antenna operating conditions include beam sweep angle, ambient temperature drift.
10. 10. An electronic device comprising the tile phased array surface of any one of claims 1-9.

Description

Ultralow noise tile type phased array surface based on silicon-based chip Technical Field The disclosure relates to the technical field of integrated circuits, in particular to an ultralow noise tile type phased array surface based on a silicon-based chip. Background Under the trend of the radio frequency phased array technology towards miniaturization, high integration and low power consumption, the tile type phased array surface becomes a mainstream architecture due to the characteristics of layered arrangement and high space utilization rate. The silicon-based technology gradually replaces gallium arsenide and other compound semiconductors with the advantages of low cost and easy mass production, and is widely applied to the fields of communication, radar and the like. Particularly in millimeter wave and microwave frequency bands, the silicon-based integrated phased array surface has realized a multi-channel beam forming function, and the performance optimization becomes an important point of industrial research. Currently, the existing tile-type phased array surface mostly adopts the architecture of a patch antenna, a coaxial-like through hole, a radio frequency feeder line and a beam forming integrated circuit (Beamformer IC, BFIC) chip. This architecture suffers from a number of problems: 1. If the BFIC chip adopts a silicon-based process, the noise coefficient of a single chip is larger, the overall noise coefficient after the link cascade is greatly influenced by the BFIC chip, and the noise coefficient of the link can be reduced by adopting the compound process chip, but the power consumption and the cost of the compound chip are high. 2. The patch antenna and BFIC chips are connected by adopting a radio frequency feeder, and the feeder loss leads to link noise, so that the noise coefficient of the phased array surface is increased. 3. The patch antenna and BFIC chip can only be subjected to fixed impedance matching on the radio frequency feed line, and in actual use, when the working condition of the antenna changes, the impedance cannot be dynamically adjusted, so that impedance mismatch is caused, and signal transmission is affected. 4. The existing architecture has no filtering device and can not filter strong interference signals. Disclosure of Invention According to the ultralow noise tile-type phased array surface based on the silicon-based chip, the ultralow noise tile-type phased array surface comprises an antenna part PCB board, an array antenna, a low noise amplifier (Low Noise Amplifier, an LNA) chip, a board-level filter, a BFIC chip and a power division network which are sequentially connected, wherein the array antenna is provided with a patch antenna, a feed point of the patch antenna is directly connected with the LNA chip through a metalized hole, the LNA chip is connected with the board-level filter through the metalized hole, the board-level filter is connected with the BFIC chip through the metalized hole, the BFIC chip is connected with the power division network through the metalized hole, and the LNA chip is integrated with a dynamic tuning matching circuit which can perform dynamic impedance matching according to the working condition of the patch antenna. In some implementations of the first aspect, BFIC chips and LNA chips are disposed on a top layer of the antenna portion PCB, the power splitting network is disposed on a second layer of the antenna portion PCB, the board-level filter is disposed on a third layer of the antenna portion PCB, and the array antenna is disposed on a bottom layer of the antenna portion PCB. In some implementations of the first aspect, the board-level filter is disposed on a third layer of the antenna portion PCB board using a strip line. In some implementations of the first aspect, the metallized hole includes a coaxial-like through hole and a blind hole, wherein a feed point of the patch antenna is directly connected with the LNA chip through the coaxial-like through hole, the LNA chip is connected with the board-level filter through the blind hole, the board-level filter is connected with the BFIC chip through the blind hole, and the BFIC chip is connected with the power distribution network through the blind hole. In some implementations of the first aspect, one BFIC chip is placed in the center of each 4 patch antennas, 4 LNA chips are surrounded around each BFIC chip, and the input end of each LNA chip coincides with two feed points of the corresponding patch antenna and is directly connected through a coaxial-like through hole. In some implementations of the first aspect, the spacing between patch antennas is determined by an operating frequency of the phased array face. In some implementations of the first aspect, the tile phased array surface further includes a non-antenna portion PCB board in which a power module, a control module, and an external interface are included; The power supply module is used for supplying power to the tile