Search

CN-121984175-A - Active equalization control chip, method, integrated circuit and computer equipment

CN121984175ACN 121984175 ACN121984175 ACN 121984175ACN-121984175-A

Abstract

The invention relates to the technical field of battery management and discloses an active equalization control chip, an active equalization control method, an integrated circuit and computer equipment, wherein the chip comprises a high-voltage MUX unit, a high-voltage power supply unit and a high-voltage power supply unit, wherein the high-voltage MUX unit comprises two buses and a switching tube pair arranged at the opposite top; the switching tube pair comprises a switching tube pair, a polarity conversion matrix, a controller and a controller, wherein the two ends of the switching tube pair are respectively connected with a battery cell sampling channel and two buses, the input end and the output end of the polarity conversion matrix are respectively connected with the buses and the positive and negative output ends, the mapping polarities between the two buses and the positive and negative bus output ends are switched according to driving signals so as to adapt to charge-discharge equalization modes, and the controller is used for acquiring battery cell voltage information, judging the required equalization modes and outputting corresponding driving signals to the polarity conversion matrix. The invention eliminates parasitic parameters of discrete devices, reduces the area of a PCB, reduces the assembly cost, improves the balance precision, realizes physical bidirectional turn-off of a pair of switching tubes arranged at the top, blocks parasitic leakage paths among different cell channels, and avoids the hidden trouble of cell short circuit caused by the conduction of a body diode in a single tube scheme.

Inventors

  • LIN TIANSHENG

Assignees

  • 东莞市达锂电子有限公司

Dates

Publication Date
20260505
Application Date
20260407

Claims (10)

  1. 1. An active equalization control chip, comprising: The high-voltage MUX unit comprises an odd channel selection bus, an even channel selection bus and a plurality of groups of switching tube pairs arranged on the top of the pairs, wherein the first end of each switching tube pair is connected with a corresponding battery cell sampling channel one by one, and the second end of each switching tube pair is correspondingly connected with the odd channel selection bus or the even channel selection bus according to the parity attribute of the battery cell sampling channel; The input end of the polarity conversion matrix is connected with the odd channel selection buses and the even channel selection buses, and the output end of the polarity conversion matrix is provided with an anode bus output end and a cathode bus output end; the polarity conversion matrix is configured to switch mapping polarities between the odd channel selection buses and/or the even channel selection buses and the positive bus output end and/or the negative bus output end according to driving signals so as to adapt to a charging or discharging equalization mode of an external circuit; And the controller is electrically connected with the high-voltage MUX unit and the polarity conversion matrix, and is used for acquiring the cell voltage information of the cell sampling channel, judging a charging or discharging equalization mode required by an external circuit based on the cell voltage information, and outputting a corresponding driving signal to the polarity conversion matrix according to the judged equalization mode so as to control the polarity conversion matrix to execute mapping polarity switching matched with the equalization mode.
  2. 2. The active equalization control chip of claim 1, wherein the pair of switching tubes arranged on the opposite sides are two NMOS tubes with drain electrodes connected; The second ends of the switch tube pairs corresponding to the odd-numbered battery cell sampling channels are connected with the odd-numbered channel selection buses, the second ends of the switch tube pairs corresponding to the even-numbered battery cell sampling channels are connected with the even-numbered channel selection buses, grid electrodes of the two NMOS tubes are commonly connected to the driving output ends of the same MUX driver, and the MUX driver is electrically connected with the controller.
  3. 3. The active equalization control chip of claim 2, wherein the polarity switching matrix comprises a full-bridge mapping circuit comprising four sets of switching tubes, the full-bridge mapping circuit being controlled by a drive signal output by the controller, wherein the odd channel select bus maps to the positive bus output and the even channel select bus maps to the negative bus output when a first set of diagonal switching tubes are closed, and wherein the odd channel select bus maps to the negative bus output and the even channel select bus maps to the positive bus output when a second set of diagonal switching tubes are closed.
  4. 4. The active equalization control chip of claim 2, wherein the controller has integrated therein a hardware sequential logic unit and a logic state machine, the logic state machine generating control signals according to built-in hard-wire logic, the control signals for controlling the gate timing of the high voltage MUX unit and outputting control signals to MUX drivers to perform the polarity mapping timing of the polarity conversion matrix.
  5. 5. The active equalization control chip of claim 1, further comprising a voltage acquisition ADC and a current sampling ADC; the input end of the voltage acquisition ADC is used for selectively acquiring the single cell voltage of the cell sampling channel or the bus voltages of the positive bus output end and the negative bus output end through the high-voltage MUX unit; And the input end of the current sampling ADC is connected with two ends of a sampling resistor arranged at the output end of the positive bus and/or the output end of the negative bus in a bridging way and used for collecting active balancing current.
  6. 6. The active equalization control chip of claim 1, further comprising an equalization enable pin and a POWER supply unit, the equalization enable pin connected to the POWER supply unit for turning off an LDO output inside the chip when the equalization enable pin is in an disabled level state, causing the chip to enter a shutdown mode.
  7. 7. An integrated multipath active equalization control method, characterized in that an active equalization control chip according to any of claims 1-6 is applied, said method comprising: the high-voltage MUX unit is controlled to gate a target cell sampling channel, and voltage signals of the target cell are correspondingly mounted on an odd channel selection bus or an even channel selection bus; Acquiring a voltage value of the target battery cell and an average voltage value of the whole group of battery cells, and calculating a deviation direction of the voltage value of the target battery cell and the average voltage value of the whole group of battery cells; determining a charge equalization mode or a discharge equalization mode required by an external circuit according to the deviation direction, and transmitting a driving signal corresponding to the equalization mode to the polarity conversion matrix; if the discharge equalization mode is adopted, the polarity conversion matrix is controlled to execute a first mapping logic, mapping polarities among the odd channel selection buses and the even channel selection buses, the positive bus output end and the negative bus output end are switched, and the polarities of the positive bus output end and the negative bus output end are consistent with the energy storage phase of the primary side of the external transformer; And if the charge equalization mode is adopted, controlling the polarity conversion matrix to execute a second mapping logic, and switching mapping polarities among the odd channel selection buses and the even channel selection buses, the positive bus output end and the negative bus output end to enable the polarities of the positive bus output end and the negative bus output end to be reversed.
  8. 8. The method of claim 7, wherein the polarity switching matrix comprises a full-bridge mapping circuit comprising four groups of switching tubes, and wherein the controller controls all switching tubes of the full-bridge mapping circuit to be synchronously turned off within a preset dead time before the polarity switching matrix performs polarity inversion.
  9. 9. An integrated circuit, comprising: The active equalization control chip of any of claims 1-6; and the primary winding of the balancing transformer is connected between the positive bus output end and the negative bus output end of the active balancing control chip, and the secondary winding of the balancing transformer is connected between the total positive electrode and the total negative electrode of the battery pack.
  10. 10. A computer device comprising a memory and a processor, wherein the processor executes a computer program stored in the memory to implement the integrated multi-path active equalization control method of claim 7 or 8.

Description

Active equalization control chip, method, integrated circuit and computer equipment Technical Field The present invention relates to the field of battery management technologies, and in particular, to an active equalization control chip, an active equalization control method, an integrated circuit, and a computer device. Background Currently, active equalization techniques in lithium Battery Management Systems (BMS) are mainly classified into inductive and transformer isolated types. The core functional modules of these equalization circuits are typically built up from a large number of discrete devices, including multi-gate switches, bi-directional DC/DC converters, logic control units, and sampling circuits. However, in the existing discrete scheme, there are some technical drawbacks. On the one hand, because the gating unit, the driving unit and the control unit are distributed in different areas of the PCB, the occupied area of the circuit is large, the miniaturization requirement of the BMS module is difficult to meet, and the complicated wiring introduces significant parasitic inductance and capacitance to influence the balance efficiency and the system EMI (ElectromagneticInterference ) performance. On the other hand, because the MOS tube has a parasitic body diode, when a plurality of strings of battery cells are gated, if the voltage difference of the battery cells is larger, a leakage path is easily formed through the body diode, even a channel is short-circuited, and the safety of the battery pack is seriously threatened. Accordingly, improvements in the art are needed. Disclosure of Invention The invention provides an active equalization control chip, an active equalization control method, an integrated circuit and computer equipment, which are used for solving the problems in the prior art. In order to achieve the above object, the present invention provides the following technical solutions: An active equalization control chip, comprising: The high-voltage MUX unit comprises an odd channel selection bus BAT1, an even channel selection bus BAT2 and a plurality of groups of switching tube pairs arranged on the top of each other, wherein the first end of each switching tube pair is connected with a corresponding battery cell sampling channel one by one, and the second end of each switching tube pair is correspondingly connected with the odd channel selection bus BAT1 or the even channel selection bus BAT2 according to the parity attribute of the battery cell sampling channel; the input end of the polarity conversion matrix is connected with the odd channel selection BUS BAT1 and the even channel selection BUS BAT2, and the output end of the polarity conversion matrix is provided with an anode BUS output end BUS+ and a cathode BUS output end BUS-; the polarity conversion matrix is configured to switch mapping polarities between the odd channel selection BUS BAT1 and/or the even channel selection BUS BAT2 and the positive BUS output end BUS+ and/or the negative BUS output end BUS-according to a driving signal so as to adapt to a charging or discharging balance mode of an external circuit; And the controller is electrically connected with the high-voltage MUX unit and the polarity conversion matrix, and is used for acquiring the cell voltage information of the cell sampling channel, judging a charging or discharging equalization mode required by an external circuit based on the cell voltage information, and outputting a corresponding driving signal to the polarity conversion matrix according to the judged equalization mode so as to control the polarity conversion matrix to execute mapping polarity switching matched with the equalization mode. Optionally, the switching tube pair arranged at the opposite top is an NMOS tube with two drains connected; the second ends of the switch tube pairs corresponding to the odd-numbered battery cell sampling channels are connected with the odd-numbered channel selection bus BAT1, the second ends of the switch tube pairs corresponding to the even-numbered battery cell sampling channels are connected with the even-numbered channel selection bus BAT2, grid electrodes of the two NMOS tubes are commonly connected to the driving output ends of the same MUX driver, and the MUX driver is electrically connected with the controller. Optionally, the polarity conversion matrix includes a full-bridge mapping circuit composed of four groups of switching tubes, wherein the full-bridge mapping circuit is controlled by a driving signal output by the controller, when a first group of diagonal switching tubes are closed, the odd channel selection BUS BAT1 is mapped to a positive BUS output terminal BUS+ and the even channel selection BUS BAT2 is mapped to a negative BUS output terminal BUS+, when a second group of diagonal switching tubes are closed, the odd channel selection BUS BAT1 is mapped to a negative BUS output terminal BUS-and the even channel selection BUS BAT2 is mapped t