CN-121984340-A - Converter transformer fault inrush current suppression circuit and method for additional thyristor pair of circuit breaker

CN121984340ACN 121984340 ACN121984340 ACN 121984340ACN-121984340-A

Abstract

The invention provides a converter transformer fault inrush current suppression circuit and a converter transformer fault inrush current suppression method for an additional thyristor pair of a circuit breaker, which relate to the field of relay protection of power systems, and the method comprises the steps of controlling current to be connected into a starting resistor after receiving an MMC starting signal, and carrying out precharge protection on a capacitor; the method comprises the steps of detecting normal operation signals, continuously obtaining current amplitude data and starting resistance temperature data, performing bypass control adjustment according to the current amplitude data and the starting resistance temperature data, pre-judging load changes, adjusting the sending time and width of trigger pulses of thyristors to obtain a smooth transition strategy, and removing the trigger pulses of thyristor pairs to inhibit fault inrush current in response to the detection of fault signals. The invention can quickly reduce the amplitude of fault inrush current, inhibit the development of the fault inrush current and ensure the correct action of the differential protection of the converter transformer.

Inventors

XUE YUTING
JI LIANGCHEN
ZHENG TAO

Assignees

华北电力大学

Dates

Publication Date: 20260505
Application Date: 20260131

Claims (10)

1. Converter transformer fault inrush current suppression circuit of additional thyristor pair of circuit breaker, use in MMC, its characterized in that includes: the output end of the positive electrode of the direct current power supply is connected with three parallel branches, and the negative electrode of the direct current power supply is grounded; the thyristor pairs are reversely connected in parallel on each parallel branch; The starting resistor is connected in parallel with the thyristor pair to form a bypass; and the circuit breaker is connected in series on each parallel branch.
2. The converter transformer fault inrush current suppression method for the additional thyristor pair of the circuit breaker, which is applied to the converter transformer fault inrush current suppression circuit for the additional thyristor pair of the circuit breaker according to claim 1, is characterized by comprising the following steps: after receiving the MMC starting signal, controlling the current to be connected into a starting resistor, and carrying out precharge protection on the capacitor; in response to the detection of the normal operation signal, continuously acquiring current amplitude data and starting resistance temperature data, and performing bypass control adjustment according to the current amplitude data and the starting resistance temperature data; the load change is prejudged, and the sending time and the width of the trigger pulse of the thyristor are adjusted to obtain a smooth transition strategy; in response to detecting the fault signal, the trigger pulse of the thyristor pair is removed for suppressing the fault inrush current.
3. The converter transformer fault inrush current suppression method of an additional thyristor pair of claim 2, wherein after receiving the MMC start signal, controlling the current to be connected to the start resistor, and performing a precharge protection on the capacitor comprises: After receiving the MMC starting signal, charging a capacitor by current through a diode in the MMC submodule; the thyristor is controlled to keep a non-conducting state, and the circuit breaker is positioned at an opening position; And current flows into the capacitor through the starting resistor, the voltage rising rate at two ends of the capacitor is monitored not to exceed a threshold value, and the capacitor is precharged and protected.
4. The converter transformer fault inrush current suppression method of claim 2, characterized by continuously obtaining current amplitude data and starting resistance temperature data in response to detecting a normal operation signal, and performing a bypass control adjustment process according to the current amplitude data and the starting resistance temperature data comprising: Continuously monitoring the voltage of the capacitor, and generating a normal operation signal when the capacitor is charged to meet the normal operation requirement; in response to detecting the normal operation signal, sending a trigger pulse to the thyristor, conducting the thyristor, closing the circuit breaker, and continuously monitoring current amplitude data and starting resistance temperature data of the starting resistor; And obtaining a bypass control instruction through a fuzzy algorithm by the current amplitude data and the starting resistance temperature data, and performing bypass adjustment.
5. The converter transformer fault inrush current suppression method of claim 4, further comprising obtaining a bypass control command from the current amplitude data and the starting resistance temperature data by a fuzzy algorithm, and performing a bypass adjustment process comprising: Taking the current amplitude and the starting resistance temperature as input variables, and carrying out reasoning calculation through a preset fuzzy rule base to obtain a reasoning result; And obtaining a control instruction from the reasoning result through deblurring, wherein the control instruction comprises the action time and the action speed of the output bypass switch.
6. The converter transformer fault current surge suppression method of a circuit breaker additional thyristor pair of claim 2, wherein said removing the trigger pulse of the thyristor pair in response to detecting the fault signal, the process for suppressing the fault current surge comprises: Detecting and comparing fault signals through a preset main fault detection sensor and an auxiliary detection circuit; When the fault signal of the main fault detection sensor is the same as the fault signal of the auxiliary detection circuit, the fault signal is true, wherein the fault signal comprises a single-phase grounding signal and an IGBT locking signal; And removing the trigger pulse of the thyristor pair, and recording faults.
7. The converter transformer fault inrush current suppression method of an additional thyristor pair of a circuit breaker of claim 2, characterized in that the process of pre-judging the load variation, adjusting the firing time and width of the thyristor trigger pulse, and obtaining a smooth transition strategy comprises: When the load changes, instantaneous change information is obtained and subjected to band-pass filtering treatment, and the filtered instantaneous change information is prejudged through an autoregressive moving average model to obtain a load change state; Presetting a thyristor trigger pulse adjustment scheme library under different load change scenes; and selecting a best matching scheme for the load change state based on cosine similarity, and adjusting the sending time and width of the trigger pulse of the thyristor as a smooth transition strategy.
8. The converter transformer fault inrush current suppression method of claim 7, wherein the process of presetting a thyristor trigger pulse adjustment scheme library under different load variation scenarios comprises: classifying the load change scene into rapid sudden increase, slow sudden decrease and periodic fluctuation; calculating the sensitivity degree of the sending time and the width of a plurality of groups of thyristor trigger pulses in the same load change scene by a local sensitivity analysis method; The sending time and width of the thyristor trigger pulse with the highest sensitivity are selected as a thyristor trigger pulse adjustment scheme; And (5) creating corresponding thyristor trigger pulse adjustment schemes for all load change scenes to form a scheme library.
9. A computer device, comprising: -at least one processor, and-a memory storing a computer program executable on the processor, characterized in that the processor, when executing the program, performs the steps of the converter transformer fault current surge suppression method of the additional thyristor pair of the circuit breaker according to any one of claims 2 to 8.
10. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, performs the steps of the converter transformer fault inrush current suppression method of a breaker additional thyristor pair according to any of claims 2 to 8.

Description

Converter transformer fault inrush current suppression circuit and method for additional thyristor pair of circuit breaker Technical Field The invention relates to the technical field of relay protection of power systems, in particular to a converter transformer fault inrush current suppression circuit and a converter transformer fault inrush current suppression method for an additional thyristor pair of a circuit breaker. Background The hybrid cascading direct current system (Hybridcascadedhigh-voltagedirectcurrent, HC-HVDC) combines the advantages of conventional direct current and flexible direct current, and the two commutation technologies of the grid commutation converter (linecommutatedconverter, LCC) and the modularized multi-level converter (multilevelmodularconverter, MMC) are cascaded on the inversion side of the hybrid cascading direct current system, so that the advantages of the hybrid cascading direct current system and the modularized multi-level converter are combined, and the hybrid cascading direct current system becomes a new direction for realizing long-distance large-capacity power transmission in recent years. The converter transformer is located between the alternating current bus and the converter, and the probability of internal faults is higher when the converter transformer works in a more complex electromagnetic environment. After a single-phase grounding fault occurs on the converter transformer valve side, a large amount of direct current component flows into the converter transformer in the valve side fault current, so that the converter transformer core is saturated and a special inrush current phenomenon, namely a fault inrush current, is generated. For the converter transformer differential protection, when the earth fault occurs in the zone at the converter transformer valve side, the converter transformer differential protection can delay action, even refusal action, due to higher content of the second harmonic in the fault inrush current, so that the safety and the stability of the system are endangered. Disclosure of Invention Aiming at the problems existing in the prior art, the invention provides a converter transformer fault inrush current suppression circuit and a converter transformer fault inrush current suppression method for an additional thyristor pair of a circuit breaker, and solves the problem that when an in-zone grounding fault occurs on the side of a converter transformer valve, the converter transformer differential protection is refused or delayed due to the influence of the fault inrush current. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: the invention provides a converter transformer fault inrush current suppression circuit of an additional thyristor pair of a circuit breaker, which is applied to MMC and comprises the following components: the output end of the positive electrode of the direct current power supply is connected with three parallel branches, and the negative electrode of the direct current power supply is grounded; the thyristor pairs are reversely connected in parallel on each parallel branch; The starting resistor is connected in parallel with the thyristor pair to form a bypass; and the circuit breaker is connected in series on each parallel branch. The invention provides a converter transformer fault inrush current suppression method of an additional thyristor pair of a circuit breaker, which is applied to a converter transformer fault inrush current suppression circuit of the additional thyristor pair of the circuit breaker, and comprises the following steps: after receiving the MMC starting signal, controlling the current to be connected into a starting resistor, and carrying out precharge protection on the capacitor; in response to the detection of the normal operation signal, continuously acquiring current amplitude data and starting resistance temperature data, and performing bypass control adjustment according to the current amplitude data and the starting resistance temperature data; the load change is prejudged, and the sending time and the width of the trigger pulse of the thyristor are adjusted to obtain a smooth transition strategy; in response to detecting the fault signal, the trigger pulse of the thyristor pair is removed for suppressing the fault inrush current. In some embodiments, after receiving the MMC start signal, controlling the current to access the start resistor, and performing precharge protection on the capacitor includes: After receiving the MMC starting signal, charging a capacitor by current through a diode in the MMC submodule; the thyristor is controlled to keep a non-conducting state, and the circuit breaker is positioned at an opening position; And current flows into the capacitor through the starting resistor, the voltage rising rate at two ends of the capacitor is monitored not to exceed a threshold value, and the capacitor is precharged and