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CN-121984446-A - High-performance dual-mode frequency multiplier circuit

CN121984446ACN 121984446 ACN121984446 ACN 121984446ACN-121984446-A

Abstract

The invention discloses a high-performance dual-mode frequency multiplier circuit. The frequency multiplier can be applied to millimeter wave bands and simultaneously outputs frequency doubling and frequency tripling signals. The circuit comprises an input balun, an improved push-push frequency doubler, a tripler based on a single-balance mixer and an output balun. The input balun converts an input single-ended fundamental wave signal into a differential signal, the improved push-push frequency doubler comprises a main push-push frequency doubler formed by field effect transistors M1/M2, a gain enhancement cross coupling pair formed by field effect transistors M3/M4, the secondary frequency doubling of the fundamental wave signal is completed, the self-mixing frequency tripler based on the single-balanced mixer completes the self-mixing frequency tripler of the fundamental wave signal by outputting matching inductors L1 and L2 and blocking capacitors C5 and C6, and the tripler signal is reserved after the subtraction operation of the two paths of signals is completed by the output balun. The scheme of the invention has the characteristics of dual-mode frequency multiplication ratio, high gain and simple structure.

Inventors

  • TONG LING
  • YANG LI
  • Sun Huanju
  • CHENG ZE
  • LIANG JIAQI
  • ZHANG DIANWEI
  • WEN WU

Assignees

  • 北京时代民芯科技有限公司
  • 北京微电子技术研究所

Dates

Publication Date
20260505
Application Date
20251030

Claims (10)

  1. 1. The high-performance dual-mode frequency multiplier circuit is characterized by comprising an input balun, a push-push frequency doubler, a tripler based on a single-balance mixer and an output balun; The input balun comprises a first blocking capacitor (C1), a second blocking capacitor (C2), a third blocking capacitor (C3) and a first transformer (TR 1), wherein the input balun is provided with an LOin input end, 2 output ends which are respectively an f0in+ output end and an f0 in-output end, the LOin input end is connected with the left end of the first blocking capacitor (C1), the right end of the first blocking capacitor (C1) is connected with the upper end of a primary coil of the first transformer (TR 1), the lower end of the primary coil of the first transformer (TR 1) is grounded, the upper end of a secondary coil of the first transformer (TR 1) is connected with the left end of the second blocking capacitor (C2), the right end of the second blocking capacitor (C2) is connected with the f0in+ output end, the lower end of the secondary coil of the first transformer (TR 1) is connected with the left end of the third blocking capacitor (C3), and the right end of the third blocking capacitor (C3) is connected with the f0 in-output end; The push-push frequency doubler comprises a first NMOS tube (M1), a second NMOS tube (M2), a third NMOS tube (M3), a fourth NMOS tube (M4), a first bias resistor (R1), a second bias resistor (R2) and a fourth blocking capacitor (C4), wherein the push-push frequency doubler is provided with 3 input ends which are respectively a first frequency doubler input end, a second frequency doubler input end and a third frequency doubler input end, the first frequency doubler input end is connected with an f0in+ output end of an input balun, the second frequency doubler input end is connected with an f0 in-output end of the input balun, the third frequency doubler input end is connected with a bias voltage end of a Vb1, the push-push frequency doubler is provided with a 2f0 output end, the first frequency doubler input end is connected with a first end of the first bias resistor (R1), a grid electrode of the first NMOS tube (M1) and a drain electrode of the third NMOS tube (M3), the second end of the first bias resistor (R1) is connected with a second frequency doubler input end of the second NMOS tube (M2), the second frequency doubler input end is connected with a second grid electrode of the second NMOS tube (M4), the second end of the second bias resistor (R2) is connected with the input end of the third frequency doubler, the source electrode of the first NMOS tube (M1) is connected with the grid electrode of the fourth NMOS tube (M4), the source electrode of the second NMOS tube (M2) is connected with the grid electrode of the third NMOS tube (M3), the source electrode of the third NMOS tube (M3) is connected with the ground, the source electrode of the fourth NMOS tube (M4) is connected with the ground, the drain electrode of the first NMOS tube (M1) is connected with the drain electrode of the second NMOS tube (M2) and then is connected with the left end of the fourth blocking capacitor (C4), and the right end of the fourth blocking capacitor (C4) is connected with the output end of the 2f 0; The frequency tripler based on the single balanced mixer comprises a fifth NMOS tube (M5), a sixth NMOS tube (M6), a third bias resistor (R3), a fourth bias resistor (R4), a fifth blocking capacitor (C5), a sixth blocking capacitor (C6), a first inductor (L1) and a second inductor (L2), wherein the frequency tripler comprises 4 input ends which are respectively a first frequency tripler input end, a second frequency tripler input end, a third frequency tripler input end and a fourth frequency tripler input end, the first frequency tripler input end is connected with an f0in+ output end of an input balun, the second frequency tripler input end is connected with an f0 in-output end of the input balun, the third frequency tripler input end is connected with a Vb2 bias voltage end, the fourth frequency tripler input end is connected with a VDD power end, the frequency tripler comprises 2 output ends which are respectively an out+ output end and an out-output end, the first frequency tripler input end is connected with a third input end of the balun, the third bias resistor (R3) is connected with a third grid electrode of the third bias resistor (R5), the third frequency tripler input end of the third bias resistor (R3) is connected with the third end of the input end of the third NMOS resistor (R3), the second end of the fourth bias resistor (R4) is connected with the input end of the third frequency multiplier, the source electrode of the fifth NMOS tube (M5) is connected with the left end of a fourth blocking capacitor (C4) in the push-push frequency multiplier after being connected with the source electrode of the sixth NMOS tube (M6), the drain electrode of the fifth NMOS tube (M5) is connected with the first end of a first inductor (L1), the first end of the fifth blocking capacitor (C5) and is connected with the out+ output end, the drain electrode of the sixth NMOS tube (M6) is connected with the first end of a second inductor (L2) and the first end of the sixth blocking capacitor (C6) and is connected with the out-output end, and the second end of the first inductor (L1), the second end of the fifth blocking capacitor (C5), the second end of the second inductor (L2) and the second end of the sixth blocking capacitor (C6) are connected and are connected with the input end of the fourth frequency multiplier; The output balun comprises a seventh blocking capacitor (C7), an eighth blocking capacitor (C8), a ninth blocking capacitor (C9) and a second transformer (TR 2), wherein the output balun is provided with 2 input ends which are respectively connected with an out+ output end and an out-output end of the tripler, the output balun is provided with a 3f0 output end, the out+ output end of the tripler is connected with the left end of the seventh blocking capacitor (C7), the right end of the seventh blocking capacitor (C7) is connected with the upper end of a primary coil of the second transformer (TR 2), the out-output end of the tripler is connected with the left end of the eighth blocking capacitor (C8), the right end of the eighth blocking capacitor (C8) is connected with the lower end of a primary coil of the second transformer (TR 2), the upper end of a secondary coil of the second transformer (TR 2) is connected with the left end of the ninth blocking capacitor (C9), the lower end of a secondary coil of the second transformer (TR 2) is connected with the right end of the ninth blocking capacitor (TR 0).
  2. 2. The high-performance dual-mode frequency multiplier circuit according to claim 1, wherein the input balun is used for converting a single-ended signal into a differential double-ended signal and providing input matching, the input balun is used for inputting a fundamental wave signal LOin generated by a local oscillator, the fundamental wave signal LOin enters the first transformer (TR 1) through the first blocking capacitor (C1), and a pair of differential signals f0in+ and f0 in-with the same amplitude and opposite phases are output after passing through the second blocking capacitor (C2) and the third blocking capacitor (C3) respectively.
  3. 3. The high-performance dual-mode frequency multiplier circuit according to claim 2, wherein the push-push frequency multiplier is used for carrying out frequency doubling on differential signals f0in+ and f 0in-to generate frequency-doubled signals 2f0, a first NMOS tube (M1) and a second NMOS tube (M2) are main push-push frequency multipliers, a third NMOS tube (M3) and a fourth NMOS tube (M4) are gain-enhanced cross-coupling pairs, and a Vb1 bias voltage end provides bias for a grid electrode of the first NMOS tube (M1) and a grid electrode of the second NMOS tube (M2) through a first bias resistor (R1) and a second bias resistor (R2), so that the first NMOS tube (M1) and the second NMOS tube (M2) are biased in a sub-threshold conductivity region to generate odd harmonic components and even harmonic components.
  4. 4. The high-performance dual-mode frequency multiplier circuit according to claim 3, wherein the tripler is used for injecting a second harmonic together with a fundamental wave into a mixer to obtain a third harmonic 3f0, a fifth NMOS tube (M5) and a sixth NMOS tube (M6) are used as the mixer, a first inductor (L1), a fifth blocking capacitor (C5), a second inductor (L2) and a sixth blocking capacitor (C6) form third harmonic output matching, a Vb2 bias voltage end provides bias for the fifth NMOS tube (M5) and the sixth NMOS tube (M6) through a third bias resistor (R3) and a fourth bias resistor (R4), and a pair of frequency tripled signals out+ and out-are output from the drain of the fifth NMOS tube (M5) and the drain of the sixth NMOS tube (M6).
  5. 5. The high-performance dual-mode frequency multiplier circuit according to claim 4, wherein the output balun is configured to change the differential double-ended signal into a single-ended signal and provide output matching, and the frequency tripled signal out+ and out-generated by the tripler is subjected to subtraction operation by passing through a seventh blocking capacitor (C7) and an eighth blocking capacitor (C8) into the second transformer (TR 2), so that the frequency tripled signal is output through a ninth blocking capacitor (C9).
  6. 6. The high performance dual mode frequency multiplier circuit of claim 1, wherein the push-push frequency doubler satisfies: I d1 ＝k 0 +k 1 (V G +V D1 )+k 2 (V G +V D1 ) 2 +k 3 (V G +V D1 ) 3 I d2 ＝k 0 -k 1 (V G +V D1 )+k 2 (V G +V D1 ) 2 -k 3 (V G +V D1 ) 3 I OUT ＝I d1 +I d2 ＝2k 0 +2k 2 (V G +V D1 ) 2 The drain current generated by the first NMOS tube (M1) is I d1 , the drain current generated by the second NMOS tube (M2) is I d2 , the sum of the drain current of the first NMOS tube (M1) and the drain current of the second NMOS tube (M2) is I OUT , the initial gate voltage swing of the first NMOS tube (M1) is V G , the initial gate voltage swing of the second NMOS tube (M2) is-V G , the drain voltage swing of the third NMOS tube (M3) is V D1 , and the drain voltage swing of the fourth NMOS tube (M4) is-V D1 ;k 0 ～k 3 , which is a constant related to a manufacturing process.
  7. 7. The high performance dual mode frequency multiplier circuit of claim 6, wherein, V D1 ＝V G1 +n·g m ·R Or alternatively V D1 ＝V G +[(n·R-1 k )g m -V TH ] The gate voltage swing of the third NMOS tube (M3) is-V G1 , the gate voltage swing of the fourth NMOS tube (M4) is V G1 , the transconductance of the first NMOS tube (M1) and the second NMOS tube (M2) is g m , the transconductance of the third NMOS tube (M3) and the transconductance of the fourth NMOS tube (M4) are n.gm, n represents the field effect tube size ratio, V TH is the threshold voltage of the first NMOS tube (M1), the second NMOS tube (M2), the third NMOS tube (M3) and the fourth NMOS tube (M4), k is a constant related to the manufacturing process, and the resistance of the first bias resistor (R1) and the second bias resistor (R2) is R.
  8. 8. The high-performance dual-mode frequency multiplier circuit according to claim 1, wherein the first bias resistor (R1) and the second bias resistor (R2) have the same resistance, the third bias resistor (R3) and the fourth bias resistor (R4) have the same resistance, the first inductor (L1) and the second inductor (L2) have the same inductance, the second blocking capacitor (C2) and the third blocking capacitor (C3) have the same capacitance, the fifth blocking capacitor (C5) and the sixth blocking capacitor (C6) have the same capacitance, the seventh blocking capacitor (C7) and the eighth blocking capacitor (C8) have the same capacitance, the first NMOS transistor (M1) and the second NMOS transistor (M2) have the same size, the third NMOS transistor (M3) and the fourth NMOS transistor (M4) have the same size, and the fifth NMOS transistor (M5) and the sixth NMOS transistor (M6) have the same size.
  9. 9. The high-performance dual-mode frequency multiplier circuit of claim 1, wherein the Vb1 bias voltage terminal provides a dc operating point for the first NMOS (M1), the second NMOS (M2), the third NMOS (M3), and the fourth NMOS (M4), and the Vb2 bias voltage terminal provides a dc operating point for the fifth NMOS (M5) and the sixth NMOS (M6).
  10. 10. The high-performance dual-mode frequency multiplier circuit according to claim 1, wherein the first transformer (TR 1) provides an input matching effect, and the second transformer (TR 2) provides an output matching effect with the first inductor (L1), the second inductor (L2), and the fifth and sixth blocking capacitors (C5, C6).

Description

High-performance dual-mode frequency multiplier circuit Technical Field The invention relates to the technical field of radio frequency integrated circuits, in particular to a high-performance dual-mode frequency multiplier circuit. Background With the continuous development of communication technology, the phenomenon of spectrum crowding occurs in the microwave frequency band, so the demand for high-performance frequency sources in the high frequency band such as millimeter wave frequency band is continuously increased. There are two ways to obtain high-performance frequency sources, one is to directly design the high-frequency signal source. This approach has low frequency stability and poor phase noise. And secondly, frequency multiplication technology is used for multiplying the stable high-performance signal in the low frequency band to the required high frequency band. In contrast, this way a high frequency signal with high output power, low phase noise and good stability can be obtained. Therefore, the high-performance frequency multiplier technology becomes a research hot spot of millimeter wave band signal sources. In recent years, the demands of communication systems and measuring instruments for multi-frequency signals are gradually increasing, and in order to simultaneously meet the demands of multiple application scenes, the integration of the two/three frequency doubling functions into the same frequency multiplier becomes a better solution than the integration of the conventional two/three frequency multipliers in the system. Currently, there are few studies on dual-mode frequency multiplier circuits, and the following problems mainly exist: (1) The frequency doubler adopts a traditional push-push structure, and has the problem of small conversion gain. (2) The frequency tripler adopts injection locking structure, and has the problems of complex structure and high design difficulty. (3) The traditional double-frequency power synthesis network synthesizes and extracts the second harmonic and the opposite-phase power to extract the third harmonic through the in-phase power synthesis, so that the problem that two kinds of frequency multiplication output cannot be obtained at the same time exists, and the practicability is poor. Disclosure of Invention The invention provides a high-performance dual-mode frequency multiplier circuit. The frequency multiplier can be applied to millimeter wave bands and can simultaneously provide output of two frequency multiplication signals, namely a frequency doubling signal and a frequency tripling signal. The frequency doubler utilizes the gain-enhanced cross coupling pair to improve the gain of the push-push frequency doubler, solves the problem of small conversion gain, and the frequency tripler part utilizes the self-mixing principle to up-convert the second harmonic and the fundamental wave, thereby effectively simplifying the circuit structure and realizing the frequency tripler function. In a first aspect, a high performance dual mode frequency multiplier circuit is provided, comprising an input balun, a push-push frequency doubler, a tripler based on a single balanced mixer, and an output balun; The input balun comprises a first blocking capacitor, a second blocking capacitor, a third blocking capacitor and a first transformer, wherein the input balun is provided with an LOin input end, the input balun is provided with 2 output ends which are respectively an f0in+ output end and an f0 in-output end, the LOin input end is connected with the left end of the first blocking capacitor, the right end of the first blocking capacitor is connected with the upper end of a primary coil of the first transformer, the lower end of the primary coil of the first transformer is grounded, the upper end of a secondary coil of the first transformer is connected with the left end of the second blocking capacitor, the right end of the second blocking capacitor is connected with the f0in+ output end, the lower end of the secondary coil of the first transformer is connected with the left end of the third blocking capacitor, and the right end of the third blocking capacitor is connected with the f0 in-output end; The push-push frequency doubler comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first bias resistor, a second bias resistor and a fourth DC blocking capacitor, wherein the push-push frequency doubler is provided with 3 input ends which are a first frequency doubler input end, a second frequency doubler input end and a third frequency doubler input end respectively, the first frequency doubler input end is connected with an f0in+ output end of an input balun, the second frequency doubler input end is connected with an f0 in-output end of the input balun, the third frequency doubler input end is connected with a Vb1 bias voltage end, the push-push frequency doubler is provided with a 2f0 output end, wherein the first frequency dou