CN-121984456-A - Power divider circuit and semiconductor substrate

CN121984456ACN 121984456 ACN121984456 ACN 121984456ACN-121984456-A

Abstract

The application provides a power divider circuit and a semiconductor substrate, which belong to the technical field of radio frequency microwaves, and comprise a first inductor and n branches which are mutually connected in parallel, wherein n is an integer larger than 1, each branch comprises a first capacitor, a first isolation sub-circuit, a second isolation sub-circuit and a second impedance transformation sub-circuit, the first capacitor and the first inductor in each branch form a first impedance transformation sub-circuit, and the second impedance transformation sub-circuit comprises a second capacitor and a second inductor.

Inventors

DING YAN
LIU JIANKUN
YANG YUNCHUN
LU YUAN
YAN YUEPENG
WANG PENGHUI
DOU YIWEN
YU XINYUAN
LIU YANCHUN

Assignees

北京赛微电子股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260123

Claims (10)

1. The power divider circuit is characterized by comprising a first inductor and n branches connected in parallel, wherein n is an integer greater than 1; Each branch circuit comprises a first capacitor, a first isolation sub-circuit, a second isolation sub-circuit and a second impedance transformation sub-circuit, wherein the first capacitor and the first inductor in each branch circuit form a first impedance transformation sub-circuit, and the second impedance transformation sub-circuit comprises a second capacitor and a second inductor; In each branch, the first end of the first capacitor is electrically connected with the first end of the first inductor, the second end of the first capacitor is electrically connected with the first end of the second capacitor and the first end of the first isolation sub-circuit, the second end of the first isolation sub-circuit is electrically connected with the second ends of the first isolation sub-circuits in the rest n-1 branches, the second end of the second capacitor is grounded, the first end of the second inductor is electrically connected with the first end of the second capacitor, the second end of the second inductor is electrically connected with the first end of the second isolation sub-circuit and the output end of the branch where the second inductor is located, and the second end of the second isolation sub-circuit is electrically connected with the second ends of the second isolation sub-circuits in the rest n-1 branches The first end of the first inductor is electrically connected with the input end of the power divider circuit, and the second end of the first inductor is grounded.
2. The power divider circuit of claim 1, further comprising an input matching circuit and n output matching sub-circuits, each of the output matching sub-circuits being disposed corresponding to one of the branches; The first end of the first inductor is electrically connected with the input end of the power divider circuit through the input matching circuit, and the input matching circuit is used for matching the equivalent impedance of the first inductor and the n branches with external source impedance; the second end of the second inductor is electrically connected with the output end of the power divider circuit through the output matching sub-circuit, and the output matching sub-circuit is used for matching the equivalent impedance of the branch circuit with the external load impedance connected with the branch circuit.
3. The power divider circuit of claim 2, wherein the input matching circuit and the output matching sub-circuit are microstrip lines.
4. The power divider circuit of claim 1, wherein the first isolation subcircuit comprises a first resistor and a third inductor, the first end of the first resistor, the first end of the third inductor, and the second end of the first capacitor are electrically connected to each other, the second end of the first resistor is electrically connected to the second end of the third inductor, and the second end of the third inductor is electrically connected to the second ends of the third inductors of the remaining n-1 branches.
5. The power divider circuit of claim 1, wherein the second isolation subcircuit comprises a second resistor and a third capacitor, the first end of the second resistor, the first end of the third capacitor, and the second end of the second inductor are electrically connected to each other, the second end of the second resistor is electrically connected to the second end of the third capacitor, and the second end of the third capacitor is electrically connected to the second ends of the third capacitors of the remaining n-1 branches.
6. A semiconductor substrate comprising the power divider circuit according to any one of claims 1 to 5; the first inductor is arranged on the central axis of the semiconductor substrate; the n branches are disposed around the same reference point of the semiconductor substrate.
7. The semiconductor substrate according to claim 6, wherein the n branches are arranged at equal intervals around the reference point of the semiconductor substrate in case where n is an odd number, and the n branches are symmetrically distributed on two mutually perpendicular axes where the reference point around the semiconductor substrate is located in case where n is an even number.
8. The semiconductor substrate according to claim 7, wherein when n is 4, the 4 branches are a first branch, a second branch, a third branch, and a fourth branch, each electronic element in the first branch and each electronic element in the second branch are distributed axisymmetrically with respect to a first axis, each electronic element in the third branch and each electronic element in the fourth branch are distributed axisymmetrically with respect to the first axis, each electronic element in the first branch and each electronic element in the second branch are distributed axisymmetrically with respect to a second axis, each electronic element in the third branch and each electronic element in the fourth branch are distributed axisymmetrically with respect to a second axis, the first axis and the second axis are perpendicular to each other, and one of the first axis and the second axis is the central axis.
9. The semiconductor substrate according to claim 8, wherein each of the 4 branches includes a first capacitor, a first resistor, a second capacitor, a second inductor, a third inductor, and a third capacitor, a line between center points of the first capacitors in the 4 branches encloses a first virtual rectangle, a line between center points of the first resistors in the 4 branches encloses a second virtual rectangle, a line between center points of the second capacitors in the 4 branches encloses a third virtual rectangle, a line between center points of the second inductors in the 4 branches encloses a fourth virtual rectangle, a line between center points of the third inductors in the 4 branches encloses a fifth virtual rectangle, and a line between center points of the third capacitors in the 4 branches encloses a sixth virtual rectangle; Wherein center points of orthographic projections of the first virtual rectangle, the second virtual rectangle, the third virtual rectangle, the fourth virtual rectangle, the fifth virtual rectangle and the sixth virtual rectangle on the semiconductor substrate coincide with orthographic projections of the reference points on the substrate of the semiconductor substrate.
10. The semiconductor substrate according to claim 9, wherein in each branch, a line between a center point of the first capacitor and a front projection of the reference point on the substrate is a first line, a line between a center point of the first resistor and a front projection of the reference point on the substrate is a second line, a line between a center point of the second capacitor and a front projection of the reference point on the substrate is a third line, a line between a center point of the second inductor and a front projection of the reference point on the substrate is a fourth line, and a line between a center point of the third inductor and a front projection of the reference point on the substrate is a fifth line; The length of the first connecting wire is smaller than that of the second connecting wire, the length of the second connecting wire is smaller than that of the fifth connecting wire, the length of the fifth connecting wire is smaller than that of the third connecting wire, the length of the third connecting wire is smaller than that of the fourth connecting wire, and the length of the fourth connecting wire is smaller than that of the sixth connecting wire.

Description

Power divider circuit and semiconductor substrate Technical Field The invention belongs to the technical field of radio frequency microwaves, and particularly relates to a power divider circuit and a semiconductor substrate. Background With the rapid development of multi-channel wireless systems such as phased array radar, MIMO (Multiple-Input Multiple-Output) communication, the conventional two-way power divider has difficulty in meeting the requirements of phased array systems and increasingly stringent requirements for multi-way power dividers. However, in the prior art, while the number of paths of the power divider is increased, the consistency of the amplitude and the phase of each output port is obviously deteriorated along with the increase of the number of paths, and the insertion loss is obviously increased. Disclosure of Invention In view of the foregoing, embodiments of the present application provide a power divider circuit and a semiconductor substrate, so as to overcome or at least partially solve the foregoing problems. According to the embodiment of the application, a power divider circuit is provided, the power divider circuit comprises a first inductor and n branches which are mutually connected in parallel, n is an integer larger than 1, each branch comprises a first capacitor, a first isolation sub-circuit, a second isolation sub-circuit and a second impedance transformation sub-circuit, the first capacitor in each branch and the first inductor form the first impedance transformation sub-circuit, the second impedance transformation sub-circuit comprises a second capacitor and a second inductor, in each branch, the first end of the first capacitor is electrically connected with the first end of the first inductor, the second end of the first capacitor is electrically connected with the first end of the second capacitor and the first end of the first isolation sub-circuit, the second end of the first isolation sub-circuit is electrically connected with the second end of the first isolation sub-circuit in the rest n-1 branches, the second end of the second capacitor is grounded, the first end of the second inductor is electrically connected with the first end of the second capacitor, the first end of the second inductor is electrically connected with the first end of the second inductor, and the second end of the second isolation sub-circuit is electrically connected with the second end of the second inductor, and the second end of the isolation sub-circuit is electrically connected with the second end of the second inductor in the rest n-1 branches. In some embodiments, the power divider circuit further comprises an input matching circuit and n output matching sub-circuits, each output matching sub-circuit is arranged corresponding to one branch, a first end of the first inductor is electrically connected with an input end of the power divider circuit through the input matching circuit, the input matching circuit is used for matching equivalent impedance of the first inductor and the n branches with external source impedance, a second end of the second inductor is electrically connected with an output end of the power divider circuit through the output matching sub-circuits, and the output matching sub-circuits are used for matching the equivalent impedance of the branches with external load impedance connected with the branches. In some embodiments, the input matching circuit and the output matching sub-circuit are each microstrip lines. In some embodiments, the first isolation subcircuit includes a first resistor and a third inductor, wherein a first end of the first resistor, a first end of the third inductor, and a second end of the first capacitor are electrically connected to each other, a second end of the first resistor is electrically connected to a second end of the third inductor, and a second end of the third inductor is electrically connected to a second end of a third inductor of the remaining n-1 branches. In some embodiments, the second isolation subcircuit includes a second resistor and a third capacitor, wherein the first end of the second resistor, the first end of the third capacitor, and the second end of the second inductor are electrically connected to each other, the second end of the second resistor is electrically connected to the second end of the third capacitor, and the second end of the third capacitor is electrically connected to the second ends of the third capacitors of the remaining n-1 branches. According to a second aspect of the embodiment of the application, a semiconductor substrate is provided, and the power divider circuit comprises the power divider circuit according to the first aspect of the embodiment of the application, wherein the first inductor is arranged on a central axis of the semiconductor substrate, and the n branches are arranged around a reference point of the semiconductor substrate. In some embodiments, n branches are arranged at e