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CN-121984458-A - Annular amplifier based on double zero compensation

CN121984458ACN 121984458 ACN121984458 ACN 121984458ACN-121984458-A

Abstract

The application discloses a double-zero compensation-based annular amplifier which comprises a main amplifier, a first zero inverter module and a second zero inverter module, wherein the main amplifier is used for receiving an input differential voltage signal, amplifying the differential voltage signal and outputting an amplified signal, and the first zero inverter module and the second zero inverter module are both connected with the main amplifier and are used for generating a first zero and a second zero and performing zero compensation on the main amplifier based on the first zero and the second zero. According to the embodiment of the application, the first zero-point inverter module and the second zero-point inverter module can be used for performing zero compensation on the main amplifier, so that the phase margin of the amplifier can be improved, the stability of the amplifier can be further improved, and the method and the device can be widely applied to the technical field of circuits.

Inventors

  • GUO MINGQIANG
  • WANG JINGXIANG
  • Sheng Shirong

Assignees

  • 澳门大学

Dates

Publication Date
20260505
Application Date
20251203

Claims (10)

  1. 1. A dual zero compensation based ring amplifier comprising: the main amplifier is used for receiving an input differential voltage signal, amplifying the differential voltage signal and outputting an amplified signal; And the first zero inverter module and the second zero inverter module are connected with the main amplifier and are used for generating a first zero and a second zero and performing zero compensation on the main amplifier based on the first zero and the second zero.
  2. 2. The dual zero compensation based ring amplifier of claim 1, wherein the main amplifier comprises a first amplifier module comprising: the first dead-zone voltage inverter comprises a first inverter module, a first dead-zone voltage inverter, a first PMOS tube and a first NMOS tube; The input end of the first inverter module is connected with the input end of the first amplifier module, the first end of the first dead zone voltage inverter is connected with the output end of the first inverter module, the second end of the first dead zone voltage inverter is connected with the control end of the first PMOS tube, the third end of the first dead zone voltage inverter is connected with the control end of the first NMOS tube, the input end of the first PMOS tube is connected with a power supply, the output end of the first PMOS tube is connected with the input end of the first NMOS tube, and the output end of the first NMOS tube is connected with the ground.
  3. 3. The dual zero compensation based ring amplifier of claim 2, wherein the main amplifier further comprises a second amplifier module comprising: the second inverter module, the second dead-zone voltage inverter, the second PMOS tube and the second NMOS tube; The input end of the second inverter module is connected with the input end of the second amplifier module, the first end of the second dead zone voltage inverter is connected with the output end of the second inverter module, the second end of the second dead zone voltage inverter is connected with the control end of the second PMOS tube, the third end of the second dead zone voltage inverter is connected with the control end of the second NMOS tube, the input end of the second PMOS tube is connected with a power supply, the output end of the second PMOS tube is connected with the input end of the second NMOS tube, and the output end of the second NMOS tube is connected with the ground.
  4. 4. A dual zero compensation based ring amplifier according to claim 3, wherein the first zero inverter module comprises: The input end of the first zero-point inverter is connected with the input end of the first inverter module, and the output end of the first zero-point inverter is connected with the output end of the first amplifier; the input end of the second zero-point inverter is connected with the output end of the first inverter module, and the output end of the second zero-point inverter is connected with the output end of the second amplifier module; The second zero inverter module includes: The input end of the third zero inverter is connected with the output end of the second inverter module, and the output end of the third zero inverter is connected with the output end of the first amplifier module; the input end of the fourth zero-point inverter is connected with the input end of the second inverter module, and the output end of the fourth zero-point inverter is connected with the output end of the second amplifier module; The first zero point inverter and the fourth zero point inverter are used for generating a pair of left half plane conjugate zero points, and the second zero point inverter and the third zero point inverter are used for disassembling the conjugate zero points and falling on a real shaft to form the first zero point and the second zero point of the two left half planes.
  5. 5. The dual zero compensation based ring amplifier of claim 3, wherein the output of the first amplifier module is located between the output of the first PMOS and the input of the first NMOS, and the output of the second amplifier module is located between the output of the second PMOS and the input of the second NMOS.
  6. 6. The dual zero compensation based ring amplifier of claim 4, wherein the first inverter module comprises: The input end of the first inverter is connected with the input end of the first zero-point inverter, the output end of the first inverter is connected with the input end of the second inverter, the input end of the second inverter is connected with the output end of the second inverter, and the output end of the second inverter is respectively connected with the input end of the first dead-zone voltage inverter and the input end of the second zero-point inverter.
  7. 7. The dual zero compensation based ring amplifier of claim 6, wherein the first dead band voltage inverter comprises: the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube; The control end of the third PMOS tube is connected with the output end of the second inverter, the input end of the third PMOS tube is connected with a power supply, the output end of the third PMOS tube is connected with the control end of the first PMOS tube, the control end of the fourth PMOS tube is connected with a first high bias voltage, the input end of the fourth PMOS tube is connected with the control end of the first PMOS tube, the output end of the fourth PMOS tube is connected with the control end of the first NMOS tube, the control end of the third NMOS tube is connected with a first low bias voltage, the input end of the third NMOS tube is connected with the control end of the first PMOS tube, the output end of the third NMOS tube is connected with the control end of the first NMOS tube, the control end of the fourth NMOS tube is connected with the output end of the second inverter, the input end of the fourth NMOS tube is connected with the control end of the first NMOS tube, and the output end of the fourth NMOS tube is connected with the ground.
  8. 8. The dual zero compensation based ring amplifier of claim 4, wherein the second inverter module comprises: The input end of the third inverter is connected with the fourth zero-point inverter, the output end of the third inverter is connected with the input end of the fourth inverter, the input end of the fourth inverter is connected with the output end of the fourth inverter, and the output end of the fourth inverter is respectively connected with the input end of the second dead-zone voltage inverter and the input end of the third zero-point inverter.
  9. 9. The dual zero compensation based ring amplifier of claim 8, wherein the second dead band voltage inverter comprises: a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; The control end of the fifth PMOS tube is connected with the output end of the fourth inverter, the input end of the fifth PMOS tube is connected with a power supply, the output end of the fifth PMOS tube is connected with the control end of the second PMOS tube, the control end of the sixth PMOS tube is connected with a second high bias voltage, the input end of the sixth PMOS tube is connected with the control end of the second PMOS tube, the output end of the sixth PMOS tube is connected with the control end of the second NMOS tube, the control end of the fifth NMOS tube is connected with a second low bias voltage, the input end of the fifth NMOS tube is connected with the control end of the second PMOS tube, the output end of the fifth NMOS tube is connected with the control end of the second NMOS tube, the control end of the sixth NMOS tube is connected with the output end of the fourth inverter, the input end of the sixth NMOS tube is connected with the control end of the second NMOS tube, and the output end of the sixth NMOS tube is connected with the ground.
  10. 10. The dual zero compensation-based ring amplifier of claim 3, the annular amplifier based on the double zero compensation is characterized by further comprising: The sampling capacitor module, the first feedback capacitor and the second feedback capacitor; The first end of the sampling capacitor module is connected with the first end of the first feedback capacitor, the second end of the sampling capacitor module is connected with the input end of the first amplifier module, the third end of the sampling capacitor module is connected with the input end of the second amplifier module, the fourth end of the sampling capacitor module is connected with the first end of the second feedback capacitor, the second end of the first feedback capacitor is connected with the output end of the first amplifier module, and the second end of the second feedback capacitor is connected with the output end of the second amplifier module.

Description

Annular amplifier based on double zero compensation Technical Field The application relates to the technical field of circuits, in particular to a circular amplifier based on double zero compensation. Background For high-speed and high-precision Analog-to-DigitalConverter, ADC Analog converters, the speed of the amplifier directly determines the overall conversion speed of the ADC, and the precision directly determines the overall conversion precision of the ADC. Therefore, in order to boost the gain of the amplifier, a ring amplifier is used. The ring amplifier uses three stages of inverters for cascading to achieve a larger gain. However, three-stage inverters introduce at least three or more poles in the feedback loop, thereby presenting a significant stability challenge. Disclosure of Invention In order to solve the technical problems, the application aims to provide the annular amplifier based on double zero compensation, which can improve the stability of the annular amplifier. To achieve the above object, an aspect of an embodiment of the present application provides a dual zero compensation-based ring amplifier, including: the main amplifier is used for receiving an input differential voltage signal, amplifying the differential voltage signal and outputting an amplified signal; And the first zero inverter module and the second zero inverter module are connected with the main amplifier and are used for generating a first zero and a second zero and performing zero compensation on the main amplifier based on the first zero and the second zero. In some embodiments, the main amplifier includes a first amplifier module comprising: the first dead-zone voltage inverter comprises a first inverter module, a first dead-zone voltage inverter, a first PMOS tube and a first NMOS tube; The input end of the first inverter module is connected with the input end of the first amplifier module, the first end of the first dead zone voltage inverter is connected with the output end of the first inverter module, the second end of the first dead zone voltage inverter is connected with the control end of the first PMOS tube, the third end of the first dead zone voltage inverter is connected with the control end of the first NMOS tube, the input end of the first PMOS tube is connected with a power supply, the output end of the first PMOS tube is connected with the input end of the first NMOS tube, and the output end of the first NMOS tube is connected with the ground. In some embodiments, the main amplifier further comprises a second amplifier module comprising: the second inverter module, the second dead-zone voltage inverter, the second PMOS tube and the second NMOS tube; The input end of the second inverter module is connected with the input end of the second amplifier module, the first end of the second dead zone voltage inverter is connected with the output end of the second inverter module, the second end of the second dead zone voltage inverter is connected with the control end of the second PMOS tube, the third end of the second dead zone voltage inverter is connected with the control end of the second NMOS tube, the input end of the second PMOS tube is connected with a power supply, the output end of the second PMOS tube is connected with the input end of the second NMOS tube, and the output end of the second NMOS tube is connected with the ground. In some embodiments, the first zero inverter module comprises: The input end of the first zero-point inverter is connected with the input end of the first inverter module, and the output end of the first zero-point inverter is connected with the output end of the first amplifier; the input end of the second zero-point inverter is connected with the output end of the first inverter module, and the output end of the second zero-point inverter is connected with the output end of the second amplifier module; The second zero inverter module includes: The input end of the third zero inverter is connected with the output end of the second inverter module, and the output end of the third zero inverter is connected with the output end of the first amplifier module; the input end of the fourth zero-point inverter is connected with the input end of the second inverter module, and the output end of the fourth zero-point inverter is connected with the output end of the second amplifier module; The first zero point inverter and the fourth zero point inverter are used for generating a pair of left half plane conjugate zero points, and the second zero point inverter and the third zero point inverter are used for disassembling the conjugate zero points and falling on a real shaft to form the first zero point and the second zero point of the two left half planes. In some embodiments, the output of the first amplifier module is located between the output of the first PMOS and the input of the first NMOS, and the output of the second amplifier module is located between the output of the seco