CN-121984459-A - Ring amplifier circuit adopting replica bias and bias enhancement technology

CN121984459ACN 121984459 ACN121984459 ACN 121984459ACN-121984459-A

Abstract

The invention discloses a ring amplifier circuit adopting a replica bias and bias enhancement technology, which comprises a first amplification stage, a second amplification stage, a third amplification stage, a replica bias loop and an output stage bias enhancement circuit, wherein in the replica bias loop, the circuit structure of a replica branch is the same as that of the second amplification stage, the circuit parameters of the replica branch and the second amplification stage form a 1/N proportion, the output stage bias enhancement circuit comprises a second amplification stage bias resistor connected in series between a PMOS (P-channel metal oxide semiconductor) and an NMOS (N-channel metal oxide semiconductor) transistor of a second amplification stage A2, and a cross connection mode of the output of the second amplification stage to the input of the third amplification stage, and the cross connection mode is that the voltage of an output node of the second amplification stage is connected to the input of the NMOS transistor of the third amplification stage, and meanwhile, the voltage of a low output node of the second amplification stage is connected to the input of the PMOS transistor of the third amplification stage. The invention realizes the comprehensive balance between stable performance and high-speed high-precision performance requirements under different process, voltage and temperature conditions by designing the replica bias loop and the output stage bias enhancement technology.

Inventors

TANG XIYUAN
WANG JINGPENG

Assignees

北京大学

Dates

Publication Date: 20260505
Application Date: 20260121

Claims (7)

1. The annular amplifier circuit is characterized by comprising a first amplifying stage, a second amplifying stage and a third amplifying stage which are sequentially cascaded, wherein the first amplifying stage, the second amplifying stage and the third amplifying stage are single-stage amplifiers based on inverters, and an amplifying structure based on dynamic inverters is adopted; the annular amplifier circuit further comprises a replica bias loop and an output stage bias enhancement circuit, wherein: The replica bias loop is used for providing stable bias voltage for the second amplifying stage and comprises a replica branch, a first auxiliary amplifier and a second auxiliary amplifier, wherein the circuit structure of the replica branch is the same as that of the second amplifying stage, and the circuit parameters of the replica branch and the second amplifying stage form a 1/N proportion; the negative input end of the first auxiliary amplifier receives a first reference common-mode voltage VCM1, and the positive input end of the first auxiliary amplifier is connected to the drain electrode of the PMOS transistor of the replica branch; the negative input end of the second auxiliary amplifier receives a second reference common-mode voltage VCM2, and the positive input end of the second auxiliary amplifier is connected to the drain electrode of the NMOS transistor of the replica branch; the output of the first auxiliary amplifier and the second auxiliary amplifier respectively control the grid electrodes of the PMOS transistor and the NMOS transistor in the replica branch to form a negative feedback loop, so that the direct current voltages of two output nodes of the replica branch are respectively stabilized at a first reference common mode voltage VCM1 and a second reference common mode voltage VCM2; The output stage bias enhancing circuit comprises a second amplifier stage bias resistor connected in series between a PMOS and an NMOS transistor of the second amplifier stage, and a cross connection mode of the second amplifier stage output to the third amplifier stage input, and is used for improving the transient response speed of the third amplifier stage, in the amplifying stage, the second amplifier stage output node voltage and the second amplifier stage low output node voltage drive the grid electrodes of the NMOS and PMOS transistors of the third amplifier stage in a cross connection mode, particularly the second amplifier stage output node voltage is connected to the NMOS transistor input of the third amplifier stage, and meanwhile the second amplifier stage low output node voltage is connected to the PMOS transistor input of the third amplifier stage, during the initial transient state of the amplifying stage, the current flowing through the second amplifier stage generates a significant voltage drop on the second amplifier stage bias resistor and is effectively overlapped to the grid source voltage of the third amplifier stage input transistor through the cross connection, and therefore the overdrive voltage of the third amplifier stage is improved.
2. The ring amplifier circuit of claim 1, wherein the ring amplifier circuit further comprises a self-zeroing capacitor for eliminating offset voltage of the first amplifier stage, a feedback capacitor for implementing closed loop switched capacitor amplification, a correlated level shift capacitor for boosting equivalent open loop gain, and a correlated level shift switch.
3. A ring amplifier circuit using replica bias and bias boosting techniques as defined in claim 1, wherein the first amplification stage uses a bootstrap input switch and the third amplification stage uses a floating inverter amplifier configuration.
4. The ring amplifier circuit of claim 1, wherein the second amplification stage comprises a PMOS transistor, an NMOS transistor, two second amplification stage bias capacitors, and a second amplification stage bias resistor, wherein the input terminal of the second amplification stage is ac-coupled to the gate of the PMOS transistor and the gate of the NMOS transistor through the two second amplification stage bias capacitors, respectively, the source of the PMOS transistor is connected to the power supply voltage, the gate thereof is connected to the first bias voltage terminal through a switch controlled by the self-zeroing clock signal, the source of the NMOS transistor is connected to ground, the gate thereof is connected to the second bias voltage terminal through a switch controlled by the self-zeroing clock signal, and the switch controlled by the phase clock signal amplified by the ring amplifier and the second amplification stage bias resistor are connected in series between the drain of the PMOS transistor and the drain of the NMOS transistor, respectively, the drain of the PMOS transistor and the drain of the NMOS transistor serve as the high output node voltage and the low output node voltage of the second amplification stage.
5. The ring amplifier circuit of claim 4 wherein the circuit parameters of the replica branch are 1/N proportional to the second amplifier stage, and in particular comprise NMOS and PMOS transistors 1/N proportional to the second amplifier stage NMOS and PMOS transistor sizes and a replica branch bias resistor having a resistance N times the second amplifier stage bias resistor.
6. The ring amplifier circuit employing replica bias and bias enhancement techniques as defined in claim 4, wherein the method of operation of the ring amplifier circuit comprises the steps of: when the self-zeroing clock signal is high, the circuit enters a self-zeroing phase, comprising: 11 Closing a switch controlled by the self-zeroing clock signal, connecting the differential input terminal of the first amplification stage to the differential output terminal of the first amplification stage, and resetting the input terminal of the ring amplifier, thereby sampling the input offset voltage of the first amplification stage and storing the input offset voltage on the self-zeroing capacitor; 12 The method comprises the steps of) activating two auxiliary amplifiers in a replica bias loop, wherein the negative input end of a first auxiliary amplifier receives a first reference common-mode voltage VCM1, and the positive input end of the first auxiliary amplifier is connected to the drain electrode of a PMOS transistor in a replica branch; 13 Using the negative feedback action of the two auxiliary amplifiers to adjust the gate voltages of the PMOS transistor and the NMOS transistor in the replica branch until the drain voltages of the PMOS transistor and the NMOS transistor in the replica branch are respectively stabilized at a first reference common-mode voltage VCM1 and a second reference common-mode voltage VCM2; 14 A PMOS transistor gate bias voltage output by the first auxiliary amplifier and an NMOS transistor gate bias voltage output by the second auxiliary amplifier are respectively applied to the gate of the PMOS transistor and the gate of the NMOS transistor of the second amplification stage A2, thereby establishing a bias current for the second amplification stage A2; when the ring amplifier amplifies the phase clock signal to a high level, the circuit enters a closed loop amplification mode, comprising: 21 Opening a switch controlled by the self-zeroing clock signal, closing a switch controlled by the amplifying phase clock signal of the ring amplifier; the first amplification stage is dynamically activated by a first amplification stage enable control signal; 22 The second amplification stage works based on bias voltage, differential output current of the second amplification stage flows through an internal second amplification stage bias resistor, and amplified differential voltage is generated at the output end of the second amplification stage; 23 The bias enhancement technology is utilized to accelerate establishment, namely, at the initial moment of an amplifying stage, a voltage drop is generated at two ends of a bias resistor by the large current output by the second amplifying stage, the high output node voltage at the positive end of the second amplifying stage with higher potential in the second amplifying stage is connected to the grid electrode of the positive NMOS input transistor of the third amplifying stage through a cross connection structure, the low output node voltage at the positive end of the second amplifying stage with lower potential is connected to the grid electrode of the PMOS input transistor of the third amplifying stage, and the same operation is carried out at the negative end, so that the overdrive voltage of the input NMOS and the PMOS transistors of the third amplifying stage is increased, and the transient output current is improved.
7. The ring amplifier circuit of claim 6, wherein in step 14) the set-up bias current Irep for the second amplification stage is represented as: Irep = (VCM1-VCM2)/(N*Rdz), Wherein VCM1 is a first reference common-mode voltage, VCM2 is a second reference common-mode voltage, N is a proportionality coefficient, rdz is the resistance of the second amplifying stage bias resistor.

Description

Ring amplifier circuit adopting replica bias and bias enhancement technology Technical Field The invention belongs to the technical field of analog integrated circuit design, relates to an operational amplifier technology used in high-speed and high-precision data converters (such as ADC) and the like, in particular to a loop amplifier circuit adopting replica bias and bias enhancement technology and a working method, and is a three-stage loop amplifier (RING AMPLIFIER) circuit technology with high-speed, high-energy efficiency and strong PVT (process, voltage and temperature) robustness. Background Operational amplifiers (Op-amps) are the most central and popular functional blocks in analog and mixed signal integrated circuits, and their performance directly determines the accuracy, speed and power consumption of the overall system. In the application of the residual amplifier stage of high-speed, high-precision data converters, especially pipelined ADCs, the operational amplifier requirements are high, requiring an extremely high balance between high gain, wide bandwidth, fast setup, low power consumption and strong robustness. Traditional operational amplifier architectures, such as Telescopic (Telecopic) and folded Cascode (Folded-Cascode) amplifiers, can provide higher DC gain and better power supply noise rejection ratio, and are classical choices for achieving high accuracy. However, as semiconductor process nodes continue to shrink, the intrinsic gain of the transistors decreases, making it difficult for these single stage architectures to maintain adequate gain at low supply voltages. To solve this problem, a multistage cascade design is usually required, but this introduces a complex frequency compensation problem, limiting the bandwidth and speed of the amplifier. More importantly, the limited output swing inherent to the cascode structure makes it inefficient in low voltage designs, making it difficult to fully utilize the power rails. In order to overcome the bottlenecks in speed and power consumption of the conventional architecture, a ring amplifier (RING AMPLIFIER) has been developed. The ring amplifier is essentially an open-loop amplifier consisting of a chain of multi-stage (typically three or five stage) inverters, with the amplification function being achieved by capacitive feedback during the closed-loop phase of operation. The high-speed and high-energy-efficiency high-output swing amplitude ring amplifier has the advantages that the inverter is used as a dynamic circuit, and can provide extremely large transient current when signals are overturned, so that the ring amplifier naturally has extremely high conversion Rate (Slew Rate), meanwhile, the ring amplifier is extremely low in static power consumption due to the characteristics of open loop and dynamic operation, the power consumption efficiency is far higher than that of a traditional amplifier, on the other hand, the ring amplifier is free from the limitation of a cascode structure, the output of the ring amplifier can be close to a power rail, and the ring amplifier is very suitable for low-voltage design. Despite the significant advantages, the existing ring amplifier technology still faces the serious challenges that the ring amplifier directly cascades the inverters, the bias points of which depend entirely on the feedback network and the threshold voltages of the transistors, lacks a well-defined definition, is extremely sensitive to fluctuations in process, voltage and temperature (PVT), results in poor performance consistency, unstable output common-mode voltage, and is difficult to apply in commercial products. In summary, the conventional high-gain operational amplifier and the existing various ring amplifiers have obvious shortcomings in realizing the process, voltage and temperature (PVT) robust bias, nanosecond fast establishment, high power consumption efficiency and common mode output voltage feedback circuit design. Therefore, there is an urgent need in the art for a new amplifier architecture that can break through the bottleneck and provide a solution with more superior overall performance. Disclosure of Invention The invention aims to solve the technical problem that the existing annular amplifier is difficult to consider between process, voltage, temperature robustness, speed and power consumption, and provides an annular amplifier circuit adopting a replica bias and bias enhancement technology, which is a novel three-stage annular amplifier circuit, and the circuit realizes the comprehensive balance between stable performance and high-speed high-precision performance requirements under different process, voltage and temperature conditions through an innovative replica bias loop and output stage bias enhancement technology. The technical scheme of the invention is as follows: A loop amplifier circuit adopting replica bias and bias enhancement technology comprises a first amplification stage, a second amplific