CN-121984483-A - High-speed low-power consumption comparator

Abstract

The invention discloses a low-power-consumption high-speed two-stage dynamic comparator for an analog-to-digital converter, relates to the technical field of integrated circuits, and aims to solve the problems that the traditional dynamic comparator is high in power consumption, limited in speed and uncontrollable in offset voltage and performance balance. The comparator comprises a pre-amplifying stage and a latch stage, wherein the pre-amplifying stage takes a PMOS transistor as an input tube and is matched with an NMOS switch tube and a PMOS active load tube to realize preliminary amplification of an input differential signal, and the latch stage adopts a PMOS latch structure instead of a traditional NMOS latch structure. The latch stage is controlled to delay activation after the pre-amplifier stage has been operated for a preset time by two delay controllable clock signals (clkb 1, clkb 2), while the current source of the pre-amplifier stage is turned off when the latch stage is activated. The delay time of the latch stage can be adjusted, offset voltage, power consumption and speed can be flexibly balanced, the performance requirements of different analog-to-digital converters can be met, and the method is suitable for scenes with high requirements on energy efficiency and speed, such as portable equipment, communication systems and the like.

Inventors

• YUAN YONGBIN
• LIAO YONG
• LIANG JIANGSHAN
• BAI JINSONG

Assignees

• 贵州木弓贵芯微电子有限公司

Dates

Publication Date

20260505

Application Date

20251204

Claims (3)

1. 1. The high-speed low-power consumption comparator is characterized in that a first-stage pre-amplifying stage and a second-stage latching stage are adopted in the structure; The first-stage preamplifier comprises an NMOS tube M1, a PMOS tube M5, a PMOS tube M4, a PMOS tube M5, a power supply Vdd, a PMOS tube M3, a PMOS tube M11, a PMOS tube M3, a PMOS tube M4, a PMOS tube M3 and a PMOS tube M4, wherein the grid electrode of the NMOS tube M1 is connected with a clock signal clk, the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube M3 is connected with the drain electrode of the PMOS tube M3, the grid electrode of the NMOS tube M2 is connected with the clock signal clk, the source electrode of the NMOS tube M2 is grounded, the drain electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M1, the source electrode of the PMOS tube M3 and the PMOS tube M4 is connected with the differential input vin+, the drain electrode of the PMOS tube; The grid electrode of the NMOS tube M6 is connected with the clock signal clk, the source electrode is grounded, the drain electrode is connected with the node Out-, and the second-stage latch stage is connected with the drain electrode of the PMOS tube M10, the grid electrode of the PMOS tube M13, the grid electrode of the NMOS tube M9 and the drain electrode of the NMOS tube M8; the grid electrode of the NMOS tube M7 is connected with a clock signal clk, the source electrode is grounded, the drain electrode is connected with a node out+, the grid electrode of the PMOS tube M11, the grid electrode of the NMOS tube M8, the grid electrode of the PMOS tube M12 and the drain electrode of the NMOS tube M9 are simultaneously connected, the grid electrode of the NMOS tube M8 is connected with the node out+, the source electrode is grounded, the grid electrode of the NMOS tube M9 is connected with the node Out-, the source electrode is grounded, the drain electrode is connected with a node out+, the grid electrode of the PMOS tube M10 is connected with a node O1-, the source electrode is connected with the drain electrode of the PMOS tube M12, the drain electrode is connected with the node out+, the source electrode of the PMOS tube M12 is connected with the drain electrode of the PMOS tube M14, the drain electrode is connected with the source electrode of the PMOS tube M10, the grid electrode of the PMOS tube M13 is connected with the node Out-, the source electrode is connected with the drain electrode of the PMOS tube M14, the grid electrode of the PMOS tube M14 is connected with the clock signal b2, the source electrode is connected with the source electrode of the PMOS tube M12, and the drain electrode of the PMOS tube M13 is connected with the source electrode of the PMOS tube M12.
2. 2. The high-speed low-power-consumption comparator according to claim 1 is characterized in that PMOS transistors M3 and M4 are adopted as input tubes and are matched with NMOS switching tubes M1 and M2 and a PMOS active load tube M5, a clock signal clk controls the switching tubes to be turned on/off so as to realize the work and stop of a pre-amplification stage, and the PMOS input tube reduces offset voltage by virtue of better matching.
3. 3. The high-speed low-power-consumption comparator according to claim 1, wherein a PMOS latch structure is used instead of a traditional NMOS latch structure, delay activation of the latch stage is realized through two paths of delay controllable clock signals of clkb1 and clkb2, the pre-amplification stage works for preset time to amplify an input signal, then the latch stage is started, and meanwhile, a current source of the pre-amplification stage is closed, so that redundant power consumption is reduced.

Description

High-speed low-power consumption comparator Technical Field The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed low-power consumption comparator. Background In the field of analog and mixed signal integrated circuits, the comparator is used as a key building module for realizing conversion from analog signals to digital signals, and the performance quality of the comparator directly determines the precision and efficiency of the whole system and is widely applied to core circuits such as high-speed analog-to-digital converters, memory sense amplifiers, data receiving interfaces and the like. With the rapid development of the internet of things, wearable equipment and mobile communication technology, unprecedented stringent requirements for high-speed and low-power consumption collaborative optimization are put forward for integrated circuits. As a key node in a signal chain, a high-speed low-power comparator has become a hot spot and difficulty of current research. Conventional high-speed comparator architectures rely primarily on latch-type structures with pre-amp stages. The structure performs preliminary amplification on weak input differential signals through the pre-amplifier so as to overcome random offset voltage caused by mismatch of the subsequent latches and effectively isolate the input signals from switching noise (namely kick-back noise) generated in a latch regeneration stage. However, this architecture faces fundamental contradictions in pursuing high speed, in that the pre-amplifier itself requires sufficient gain and bandwidth to ensure response speed and suppress offset, but this typically requires consuming a large static bias current, resulting in a significant increase in power consumption, and the additional cascaded delay it introduces can be a bottleneck to increase overall comparison speed. In addition, to achieve high input impedance and low offset, preamplifiers often employ differential pair-tube loads whose static power consumption persists throughout the comparison period, which can result in significant energy waste in intermittently operating systems (e.g., successive approximation ADCs). In recent years, researchers have proposed many improvements to achieve a better tradeoff between speed, power consumption, accuracy, and noise. For example, offset storage techniques, introducing charge pump input structures to boost gain, or pipelined comparison strategies that design multistage dynamic amplifiers to work interleaved with latches. However, these techniques often come at the cost of increased circuit complexity, clock phase overhead, or placement and routing difficulties. In addition, as the semiconductor process node continues to evolve toward the nanometer scale, the supply voltage is continuously reduced, which makes the design of the comparator face avalanche-like challenges, such as low voltage, reduced intrinsic gain of the transistor, resulting in degradation of the amplifier stage performance, reduced signal swing, resulting in lower tolerance of the comparator to noise and offset, and the short channel effect of the transistor exacerbates the process deviation and instability of the performance. Therefore, the prior art clearly shows that developing an innovative comparator solution, which can fundamentally and cooperatively optimize the speed and the power consumption without remarkably increasing the complexity of the circuit and depending on expensive calibration technology, has good offset characteristics, low kick noise and strong robustness to advanced low-voltage technology, and is an urgent technical problem to be solved in the industry. The present invention is directed to a novel circuit architecture and a novel method of operation, which break through the performance bottleneck of the prior art. Disclosure of Invention The invention provides a high-speed low-power consumption comparator. The invention provides a high-speed low-power consumption comparator which specifically comprises a first-stage pre-amplifying stage and a second-stage latching stage, wherein a PMOS transistor is used as an input tube and matched with an NMOS switching tube and a PMOS active load tube. The clock signal clk controls the switching tube to be turned on/off to realize the work and stop of the pre-amplification stage, the PMOS input tube helps to reduce offset voltage by virtue of better matching, a PMOS latch structure is innovatively used instead of traditional NMOS latch, the delay activation of the latch stage is realized by two paths of delay controllable clock signals of clkb1 and clkb2, the pre-amplification stage works for preset time to amplify the input signal, then the latch stage is started, and meanwhile, the pre-amplification stage current source is turned off to reduce redundant power consumption. The low power consumption of the pre-amplifier stage enables us to design the input transistors (PMOS trans