CN-121984494-A - Clock frequency detection system and method based on clock edge alignment detection

CN121984494ACN 121984494 ACN121984494 ACN 121984494ACN-121984494-A

Abstract

The invention relates to the technical field of digital clock signal processing, in particular to a clock frequency detection system and method based on clock edge alignment detection, wherein the system comprises a working state monitoring module, a sampling period counting module, a clock sampling module, a state judging and changing module and an index generating and outputting module; the system is in the signal release of normal operating condition through operating condition monitoring module, will high frequency clock signal input to operating condition monitoring module, and the system is through the periodic sampling of low frequency clock control sampling period, and the high level quantity in the statistics sampling period judges high frequency clock state change to judge that low frequency clock rising edge aligns with high frequency clock rising edge, outputs corresponding phase index value. The invention is realized by adopting pure digital logic, has anti-jitter capability, can accurately identify the phase of the high-frequency clock, and has the advantages of simple structure, high precision and strong portability.

Inventors

QIAN QING
CHU MENGYUAN
SHI TINGYI
LIN XINNAN
ZHANG XIAOQIANG
PENG ZHIWEI
FU JIE
GAO XIAOFANG
YANG XIAOYU
LI LIANG
YANG JUNJIE

Assignees

安徽工程大学
中国电子科技集团公司第二十四研究所

Dates

Publication Date: 20260505
Application Date: 20251230

Claims (9)

1. The clock frequency detection system based on clock edge alignment detection is characterized by comprising a working state monitoring module, a sampling period counting module, a clock sampling module, a state judging and changing module and an index generating and outputting module, wherein the output of the index generating and outputting module comprises a phase index value and an index effective signal; the working state monitoring module is used for detecting the working state of the system and outputting a normal working signal of the system to the sampling period counting module, the clock sampling module, the state judging and changing module and the index generating and outputting module; The sampling period counting module is used for tracking the sampling period based on the input low-frequency clock signal and the system normal working signal, and outputting a sampling period ending signal when the count value in the current sampling period reaches a preset maximum value; The clock sampling module is used for sampling the high-frequency clock signal in each sampling period, counting the high level number of the high-frequency clock signal in the sampling period, and transmitting the high level number as an input signal to the state judging and changing module; the state judging and changing module judges the state of the high-frequency clock signal in the sampling period and detects the state change based on the high-level quantity, and when the effective jump of the state is detected, the state jump signal is output and the working state monitoring module is triggered to adjust the normal working signal of the system; and the index generation and output module generates a final phase index value based on the high level quantity and the state change information, and continuously outputs the final phase index value after the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock.
2. The clock frequency detection system based on clock edge alignment detection of claim 1, wherein the sampling period counting module triggers a counting operation at each rising edge of the low frequency clock, and generates the sampling period end signal when the sampling count value reaches the preset maximum value, the sampling period end signal characterizing that sampling of one sampling period is completed.
3. The clock frequency detection system based on clock edge alignment detection of claim 2, wherein the end of sampling period signal is generated by bitwise ANDed with the sample count value, and wherein the end of sampling period signal is high when the sample count value is an all 1 binary number.
4. The clock frequency detection system based on clock edge alignment detection of claim 1, wherein the process of outputting a state transition signal when the state determination and change module determines a valid transition comprises: presetting a first threshold value and a second threshold value, wherein the first threshold value is smaller than the second threshold value, judging that a high-frequency clock signal in a current sampling period is in an all-0 state when the high level number is smaller than the first threshold value, judging that the high-frequency clock signal in the current sampling period is in an all-1 state when the high level number is larger than the second threshold value, and judging that the high-frequency clock signal in the current sampling period is in an edge state when the high level number is between the first threshold value and the second threshold value, wherein the edge state is a transition state of 0 and 1; And comparing the current state with the last state of the last sampling period to judge whether the effective jump occurs or not, and generating the state jump signal.
5. The clock frequency detection system based on clock edge alignment detection of claim 4, wherein the index generation and output module determines that a rising edge of a low frequency clock is aligned with a rising edge of a high frequency clock when the state transition signal characterizes an all 0 state transition to an all 1 state or an edge state transition to an all 1 state.
6. The clock frequency detection system based on clock edge alignment detection of claim 1, wherein the index generation and output module comprises a current index register and an effective index register, wherein the current index register is used for storing a current index value generated currently, and the current index value is increased by 1 per sample period when the system is in a normal working state; When the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, the effective index register stores the value obtained by subtracting 1 from the current index value as an effective index value; The index valid signal is used for indicating whether the output index value is valid or not, and the phase index value is the final output of the system.
7. The clock frequency detection system based on clock edge alignment detection of claim 6, wherein the output of the phase index value is controlled by the system normal operation signal such that the phase index value is the lower five bits of the current index value when the system normal operation signal is high, the phase index value is the lower five bits of the valid index value when the system normal operation signal is low, the level of the system normal operation signal is controlled by the state transition signal such that the system normal operation signal is low when the state transition signal characterizes an "all 0 state transition to an all 1 state" or an "edge state transition to an all 1 state", the current index value stops self-increasing when the system normal operation signal is low, and the index valid signal is high.
8. The clock frequency detection system based on clock edge alignment detection according to claim 1, wherein the working state monitoring module controls a system operation state through the system normal working signal, wherein after the system is asynchronously reset, the system normal working signal is set to be high level to represent that the system is in a working state, when the working state monitoring module detects that the state jump signal represents that the state jump signal is in an all 0 state to an all 1 state or in an edge state to an all 1 state, the system normal working signal is set to be low level, the system stops index updating, when the system normal working signal is in a low level, the index valid signal is set to be high level, and the phase index value outputs the low five bits of the valid index value.
9. A clock frequency detection method based on clock edge alignment detection, the method comprising the steps of: s1, initializing a system, namely resetting the system through an asynchronous reset signal, generating and outputting a high-level system normal working signal by a working state monitoring module, representing that the system enters a working state, and initializing registers of a sampling period counting module, a clock sampling module, a state judging and changing module and an index generating and outputting module to a preset initial state; S2, sampling period counting, namely counting at each rising edge of a low-frequency clock based on a low-frequency clock signal and a high-level system normal working signal by a sampling period counting module, and outputting a sampling period ending signal when the count value reaches a preset maximum value to characterize completion of one sampling period; S3, sampling and counting the high-frequency clock, namely continuously sampling the high-frequency clock signal in each sampling period by a clock sampling module in the normal working period of the system, counting the high-level number of the high-frequency clock signal in the sampling period, and transmitting the high-level number to a state judging and changing module; S4, state judgment and jump detection, wherein the state judgment and change module judges the state of the high-frequency clock signal in the current sampling period based on the high level quantity, compares the current state with the state of the last sampling period, and detects the state change in the period of the adjacent sampling period; S5, adjusting the working state of the system, namely adjusting the level of a normal working signal of the system after the working state monitoring module receives the state jump signal, and representing that the system stops index updating; And S6, generating an index value based on the high level quantity and the state change information by the index generation and output module, outputting a corresponding index value according to the level of a normal working signal of the system, and when the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, outputting an effective index value obtained by subtracting 1 from the current index value by the index generation and output module as a final phase index value, continuously outputting the final phase index value, and setting an index effective signal to indicate that the phase index value is effective.

Description

Clock frequency detection system and method based on clock edge alignment detection Technical Field The invention relates to the technical field of digital clock signal processing, in particular to a clock frequency detection system and method based on clock edge alignment detection. Background In a high-speed digital system, the synchronization and phase detection of clock signals are one of key technologies for ensuring the stable operation of the system, and particularly in the scenes of 5G communication, high-speed storage and the like, along with the continuous improvement of the system frequency, the traditional clock detection method is difficult to meet the accurate identification requirement of the phase relation between a high-frequency clock and a low-frequency reference clock. The current high-frequency clock detection technology has obvious defects that the analog phase-locked loop (PLL) and the delay-locked loop (DLL) are weak in anti-interference, sensitive to high-frequency clock jitter, poor in stability and poor in portability, the existing digital scheme can only roughly measure frequencies, cannot distinguish 32 or more fine phases, is easy to misjudge alignment due to non-closed logic loops, and in addition, most schemes are low in functional integration level, lack of state monitoring and serious in resource waste. In summary, the prior art has the problems of weak jitter resistance, low precision, poor portability and insufficient integration level, and a high-frequency clock edge alignment and frequency detection scheme with pure digital logic, high precision and strong interference resistance is needed. Disclosure of Invention Therefore, the invention aims to provide a clock frequency detection system and method based on clock edge alignment detection, so as to solve the problems of weak jitter resistance, low precision, poor portability and insufficient integration level in the prior art. Based on the above purpose, the invention provides a clock frequency detection system based on clock edge alignment detection, which comprises a working state monitoring module, a sampling period counting module, a clock sampling module, a state judging and changing module and an index generating and outputting module, wherein the output of the index generating and outputting module comprises a phase index value and an index effective signal; the working state monitoring module is used for detecting the working state of the system and outputting a normal working signal of the system to the sampling period counting module, the clock sampling module, the state judging and changing module and the index generating and outputting module; The sampling period counting module is used for tracking the sampling period based on the input low-frequency clock signal and the system normal working signal, and outputting a sampling period ending signal when the count value in the current sampling period reaches a preset maximum value; The clock sampling module is used for sampling the high-frequency clock signal in each sampling period, counting the high level number of the high-frequency clock signal in the sampling period, and transmitting the high level number as an input signal to the state judging and changing module; the state judging and changing module judges the state of the high-frequency clock signal in the sampling period and detects the state change based on the high-level quantity, and when the effective jump of the state is detected, the state jump signal is output and the working state monitoring module is triggered to adjust the normal working signal of the system; and the index generation and output module generates a final phase index value based on the high level quantity and the state change information, and continuously outputs the final phase index value after the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock. Preferably, the sampling period counting module triggers a counting operation at each rising edge of the low-frequency clock, and generates the sampling period end signal when the sampling count value reaches the preset maximum value, wherein the sampling period end signal characterizes that sampling of one sampling period is completed. Preferably, the sampling period end signal is generated by performing bit-wise AND operation on the sampling count value, and when the sampling count value is an all-1 binary number, the sampling period end signal is at a high level. Preferably, when the state determining and changing module determines that the transition is valid, the process of outputting the state transition signal includes: presetting a first threshold value and a second threshold value, wherein the first threshold value is smaller than the second threshold value, judging that a high-frequency clock signal in a current sampling period is in an all-0 state when the high level number is smaller than the first threshold value, judgi