CN-121984495-A - Phase frequency detector based on capture acceleration and noise suppression dual-mode self-adaptive switching

CN121984495ACN 121984495 ACN121984495 ACN 121984495ACN-121984495-A

Abstract

The invention discloses a phase frequency detector based on capture acceleration and noise suppression dual-mode self-adaptive switching, which adopts a duty ratio shaping module to shape a reference signal and a feedback signal, reduces the duty ratio, expands the working range of a capture acceleration mode, is beneficial to reducing the locking time of a loop, utilizes a mode controller to detect the phase difference of the reference shaping signal and the feedback shaping signal, judges the locking state, controls a reset path to switch between the capture acceleration mode and the noise suppression mode, eliminates a high phase discrimination blind area introduced by the noise suppression mode, and expands the phase discrimination range of the phase frequency detector. The invention adopts the reset path as the capture acceleration path and the noise suppression path, the capture acceleration path adopts the input delay sampling technology to counteract the inherent delay of the reset signal during generation and transmission, effectively expands the phase discrimination range, reduces the phase discrimination dead zone of the phase discriminator, optimizes the time sequence of the generation of the reset signal by the noise suppression path, and expands the charging and discharging time of the loop.

Inventors

LU QIJUN
CHEN YIFU
Zhan Runnan
ZHANG TAO
AN XIN
LIU BEI
ZHU ZHANGMING

Assignees

西安电子科技大学

Dates

Publication Date: 20260505
Application Date: 20251217

Claims (10)

1. A phase frequency detector based on acquisition acceleration and noise suppression dual-mode adaptive switching, comprising: The system comprises a duty ratio shaping module, a mode controller, a capture acceleration path, a noise suppression path, a data selection module and an edge detection module, The duty ratio shaping module is used for adjusting the duty ratio of the reference signal REF and the feedback signal DIV of the frequency divider in the phase-locked loop and outputting a reference shaping signal and a feedback shaping signal; The mode controller synchronously detects a reference shaping signal and a feedback shaping signal in each period, confirms a working mode after the current period is ended according to the locking state of the current period, and automatically controls a reset path of the phase frequency detector to correspondingly switch to a capture acceleration path or a noise suppression path according to the working mode and correspondingly outputs a locking signal or a suppression signal; The capture acceleration path reduces the phase difference between the reference shaping signal and the feedback shaping signal based on the detection pulse signal output by the edge detection module and outputs a first reset pulse signal in a capture acceleration mode; the noise suppression path generates a second reset pulse signal based on the detection pulse signal output by the edge detection module in a noise suppression mode, wherein the second reset pulse signal comprises a second reference reset pulse signal and a second feedback reset pulse signal; the data selection module selectively conducts a first reset pulse signal or a second reset pulse signal according to a locking signal or a suppression signal output by the mode controller, so as to realize the self-adaptive switching of the phase frequency detector between two working modes; The edge detection module converts the phase difference between the reference shaping signal and the feedback shaping signal into a detection pulse signal to be output under the control of the first reset pulse signal or the second reset pulse signal.
2. The phase frequency detector based on the capture acceleration and noise suppression dual-mode adaptive switching of claim 1, wherein the duty cycle shaping module comprises: the first duty ratio shaper and the second duty ratio shaper are identical in structure; Any one of the first duty cycle shaper and the second duty cycle shaper comprises: a first D flip-flop, a first exclusive-OR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor, The clock input end of the first D trigger is used as the input end of the duty ratio shaper, the data input end D is connected with the self inverting output end QB, and the in-phase output end Q is connected with the first input end of the first exclusive-OR gate; The second input end of the first exclusive-OR gate is connected with the output end of the sixth inverter, and the output end is used as the output end of the duty ratio shaper; the input end of the first inverter is connected with the in-phase output end Q of the first D trigger, and the output end of the first inverter is connected with the input end of the second inverter; the output end of the second inverter is connected with the input end of the third inverter; the output end of the third inverter is connected with the input end of the fourth inverter; The output end of the fourth inverter is connected with the input end of the fifth inverter; the output end of the fifth inverter is connected with the input end of the sixth inverter; the first end of the first capacitor is connected with the output end of the first inverter, and the second end of the first capacitor is connected with the second end of the second capacitor; the first end of the second capacitor is connected with the output end of the second inverter, and the second end of the second capacitor is connected with the second end of the third capacitor; the first end of the third capacitor is connected with the output end of the third inverter, and the second end of the third capacitor is grounded; the first end of the fourth capacitor is connected with the output end of the fourth inverter, and the second end of the fourth capacitor is grounded; the first end of the fifth capacitor is connected with the output end of the fifth inverter, and the second end of the fifth capacitor is connected with the second end of the fourth capacitor; the first end of the sixth capacitor is connected with the output end of the sixth inverter, and the second end of the sixth capacitor is connected with the second end of the fifth capacitor.
3. The phase frequency detector based on capture acceleration and noise suppression dual-mode adaptive switching of claim 2, wherein the duty cycle shaping module adjusts the duty cycle of the reference signal REF and the feedback signal DIV of the frequency divider in the phase-locked loop, and outputs a reference shaped signal and a feedback shaped signal, comprising: The first duty ratio shaper is utilized to carry out frequency division and delay processing on the reference signal REF, so that the duty ratio is adjusted while the frequency is kept unchanged, and the reference shaping signal is output; and frequency division and delay processing are carried out on the feedback signal DIV by using a second duty ratio shaper, so that the duty ratio is adjusted while the frequency is kept unchanged, and a feedback shaping signal is output.
4. A phase frequency detector based on acquisition acceleration and noise suppression dual mode adaptive switching as defined in claim 1, wherein said mode controller comprises: a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first NOR gate, a second NOR gate and a seventh inverter, The clock input end of the second D trigger is used as a first input end of the mode controller, a reference shaping signal is accessed, the data input end D is connected with the clock input end of the third D trigger, and the in-phase output end Q is connected with the first input end of the first NOR gate; The clock input end of the third D trigger is connected with the second input end serving as the mode controller, is connected with the feedback shaping signal, the data input end D is connected with the clock input end of the second D trigger, and the in-phase output end Q is connected with the second input end of the first NOR gate; the output end of the first NOR gate is connected with the data input end D of the fourth D trigger; The first input end and the second input end of the second NOR gate are used as feedback input ends of the mode controller, connected with detection pulse signals, and the output end of the second NOR gate is connected with the input end of the seventh inverter; the output end of the seventh inverter is connected with the clock input end of the fourth D trigger; the in-phase output terminal Q of the fourth D trigger is used as the output terminal of the mode controller.
5. The phase frequency detector based on dual-mode adaptive switching of acquisition acceleration and noise suppression of claim 1, wherein the acquisition acceleration path comprises: A first NAND gate, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a first asynchronous reset D flip-flop, and a second asynchronous reset D flip-flop, The first input end and the second input end of the first NAND gate are used as feedback input ends of the capture acceleration path, are connected with detection pulse signals, and the output ends of the first NAND gate are connected with the input end of the tenth inverter; The input end of the eighth inverter is used as a first input end of a capturing acceleration path, is connected with a reference shaping signal, and the output end of the eighth inverter is connected with the input end of the ninth inverter; The output end of the ninth inverter is connected with the data input end of the first asynchronous reset D trigger; the clock input end of the first asynchronous reset D trigger is connected with the output end of the tenth inverter, the reset end is connected with the output end of the twelfth inverter, the inverted output end is used as a first output end of a capture acceleration path, and a first reference reset pulse signal is output; The clock input end of the second asynchronous reset D trigger is connected with the output end of the tenth inverter, the data input end of the second asynchronous reset D trigger is connected with the output end of the fourteenth inverter, the reset end of the second asynchronous reset D trigger is connected with the output end of the twelfth inverter, the inverting output end of the second asynchronous reset D trigger is used as a second output end of a capturing acceleration path, and a first feedback reset pulse signal is output; the output end of the tenth inverter is connected with the input end of the eleventh inverter; the output end of the eleventh inverter is connected with the input end of the twelfth inverter; The input end of the thirteenth inverter is used as a second input end of the capturing acceleration path, is connected with the feedback shaping signal, and the output end of the thirteenth inverter is connected with the input end of the fourteenth inverter.
6. The phase frequency detector based on dual-mode adaptive switching of acquisition acceleration and noise suppression of claim 1, wherein the noise suppression path comprises: a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a second NAND gate, a third NAND gate, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor, wherein, The input end of the fifteenth inverter is used as a first input end of a noise suppression path, and the output end of the fifteenth inverter is connected with the input end of the sixteenth inverter; the output end of the sixteenth inverter is connected with the first input end of the third NAND gate; the input end of the seventeenth inverter is used as a second input end of the noise suppression path, and the output end of the seventeenth inverter is connected with the input end of the eighteenth inverter; the output end of the eighteenth inverter is connected with the second input end of the second NAND gate; The first end of the seventh capacitor is connected with the output end of the fifteenth inverter, and the second end of the seventh capacitor is grounded; The first end of the eighth capacitor is connected with the output end of the sixteenth inverter, and the second end of the eighth capacitor is connected with the second end of the seventh capacitor; The first end of the ninth capacitor is connected with the second end of the seventh capacitor, and the second end of the ninth capacitor is connected with the output end of the seventeenth inverter; the first end of the tenth capacitor is connected with the first end of the ninth capacitor, and the second end of the tenth capacitor is connected with the output end of the eighteenth inverter; the first input end of the second NAND gate is connected with the input end of the fifteenth inverter, and the output end is used as the first output end of the noise suppression path and outputs a second reference reset pulse signal; And a second input end of the third NAND gate is connected with an input end of the seventeenth inverter, and an output end of the third NAND gate is used as a second output end of the noise suppression path and outputs a second feedback reset pulse signal.
7. The phase frequency detector based on the capture acceleration and noise suppression dual-mode adaptive switching of claim 1, wherein the data selection module comprises: The first data selector and the second data selector are identical in structure; Any one of the first data selector and the second data selector includes: A first transistor, a second transistor, a third transistor, a fourth transistor, a nineteenth inverter, and a twentieth inverter, wherein, The source electrode of the first transistor is connected with the input end of the twentieth phase inverter, the grid electrode is used as a first input end of the data selector, the output signal of the mode controller is connected, and the drain electrode is used as a second input end of the data selector; The source electrode of the second transistor is connected with the source electrode of the first transistor, the grid electrode of the second transistor is connected with the output end of the nineteenth inverter, and the drain electrode of the second transistor is connected with the drain electrode of the first transistor; The source electrode of the third transistor is connected with the input end of the twenty-second inverter, the grid electrode of the third transistor is connected with the grid electrode of the second transistor, and the drain electrode of the third transistor is used as the third input end of the data selector; the source electrode of the fourth transistor is connected with the source electrode of the third transistor, the grid electrode of the fourth transistor is connected with the grid electrode of the first transistor, and the drain electrode of the fourth transistor is connected with the drain electrode of the third transistor; an input end of the nineteenth inverter is connected with a grid electrode of the fourth transistor; The output end of the twenty-first inverter is used as the output end of the data selector; A second input end of the first data selector is connected with a second reference reset pulse signal, and a third input end of the first data selector is connected with a first reference reset pulse signal; And a second input end of the second data selector is connected with a second feedback reset pulse signal, and a third input end of the second data selector is connected with the first feedback reset pulse signal.
8. The phase frequency detector based on the capture acceleration and noise suppression dual-mode adaptive switching of claim 1, wherein the edge detection module comprises: A third asynchronous reset D flip-flop, a fourth asynchronous reset D flip-flop, a twenty-first inverter, a twenty-second inverter, a twenty-third inverter and a twenty-fourth inverter, wherein, The clock input end of the third asynchronous reset D trigger is used as a first input end of the edge detection module, is connected with a reference shaping signal, the reset end is used as a first control end of the edge detection module, is connected with an output signal of a first data selector in the data selection module, and the in-phase output end is connected with the input end of the twenty-first phase inverter; the clock input end of the fourth asynchronous reset D trigger is used as a second input end of the edge detection module, connected with a feedback shaping signal, the reset end is used as a second control end of the edge detection module, connected with an output signal of a second data selector in the data selection module, and the in-phase output end is connected with the input end of a twenty-third inverter; The output end of the twenty-first inverter is connected with the input end of the twenty-second inverter; The output ends of the twenty-second inverter and the twenty-fourth inverter are used as the output ends of the edge detection module; The output end of the thirteenth inverter is connected with the input end of the twenty-fourth inverter.
9. The phase frequency detector based on the capture acceleration and noise suppression dual-mode adaptive switching as claimed in claim 1, wherein the mode controller synchronously detects the reference shaping signal and the feedback shaping signal in each period, confirms the working mode after the current period is finished according to the locking state of the current period, automatically controls the reset path of the phase frequency detector to correspondingly switch to the capture acceleration path or the noise suppression path according to the working mode, and correspondingly outputs the locking signal or the suppression signal, and comprises: the mode controller carries out cross sampling on the reference shaping signal and the feedback shaping signal, judges the phase difference of the reference shaping signal and the feedback shaping signal in each period, switches the reset path of the phase frequency detector to a capture acceleration path after the current period is ended when the phase difference exceeds a preset difference value, enters a capture acceleration mode, outputs a locking signal, switches the reset path of the phase frequency detector to a noise suppression path after the current period is ended when the phase difference is smaller than the preset difference value, enters a noise suppression mode, and outputs a suppression signal.
10. The phase frequency detector based on the capture acceleration and noise suppression dual-mode adaptive switching as set forth in claim 7, wherein the data selection module selectively turns on the first reset pulse signal or the second reset pulse signal according to the lock signal or the suppression signal output by the mode controller, to realize the adaptive switching of the phase frequency detector between two operation modes, and the phase frequency detector comprises: The data selection module conducts a first reference reset pulse signal according to the locking signal, and the second data selector conducts a first feedback reset pulse signal, outputs the first feedback reset pulse signal to the edge detection module and enters a capture acceleration mode; The data selection module conducts a second reference reset pulse signal according to the suppression signal, the second data selector conducts a second feedback reset pulse signal, outputs the second feedback reset pulse signal to the edge detection module, and enters a noise suppression mode.

Description

Phase frequency detector based on capture acceleration and noise suppression dual-mode self-adaptive switching Technical Field The invention belongs to the technical field of millimeter wave integrated circuits, and particularly relates to a phase frequency detector based on capture acceleration and noise suppression dual-mode self-adaptive switching. Background The phase-locked loop is used as an indispensable core module in a wireless communication system, and the performance quality of the phase-locked loop directly determines important indexes such as sensitivity, noise coefficient, linearity and the like of a wireless transceiver. Key metrics for measuring phase-locked loop performance include phase noise, lock time, reference spurs, output frequency range, frequency resolution, etc. With the rising application demands of mobile communication, wireless local area network, satellite communication, etc., the requirements of wireless communication systems on data transmission rate and channel bandwidth are continuously increasing. On one hand, the development of high-order modulation techniques such as 1024-QAM is promoted, in a high-order modulation system, signals are very sensitive to phase jitter, and the phase noise of a phase-locked loop directly influences the error vector amplitude and the receiving sensitivity of the system, so that the communication quality is restricted. On the other hand, as low-frequency spectrum resources are increasingly strained, a communication system is gradually moved to a millimeter wave band, and high propagation loss of millimeter waves is compensated by utilizing a large-scale MIMO and beam forming technology, so that higher requirements on phase noise and locking time of a phase-locked loop are provided. Therefore, the high performance millimeter wave phase locked loop with low phase noise and fast locking has been a popular research direction in the field of radio frequency integrated circuits for many years. In the field of high-performance phase-locked loop research, a technical scheme for realizing low phase noise comprises a module circuit for designing low phase noise and an architecture for improving a phase-locked loop. In the former, out-of-band noise is dominated by the voltage-controlled oscillator, while in-band noise is dominated by the phase frequency detector and the charge pump, and current research is mainly focused on designing and implementing a high-performance voltage-controlled oscillator, thereby reducing out-of-band phase noise of the phase-locked loop. However, when the frequency comes to the millimeter wave band, the marginal effect of the research high-performance voltage-controlled oscillator is more obvious because the increase of the frequency division ratio improves the contribution of the in-band phase noise. For the latter, there have been many new architectures proposed in recent years for high performance phase locked loops that can achieve excellent phase noise performance, representative architectures include sampling phase locked loops, sub-sampling phase locked loops, injection locked phase locked loops, and the like. However, these phase-locked loops are greatly affected by PVT, the sampling phase-locked loop has high power consumption, the phase discrimination range of the sub-sampling phase-locked loop is narrow, the phase-locked loop is easy to lose lock, and the injection locking phase-locked loop is not suitable for working in a high frequency band. The technical scheme for realizing the quick locking comprises a dynamic bandwidth technology, a precharge technology, a fractional frequency division technology and the like. The locking time of the phase-locked loop is inversely related to the loop bandwidth, the dynamic bandwidth technology switches the loop to a large bandwidth in the phase-locked loop capturing stage, the loop locking is accelerated, the loop is switched to a small bandwidth after the loop is locked, and the phase noise is optimized. The precharge technique applies an initial voltage to the loop filter at the start-up or frequency hopping of the phase locked loop, and tunes the voltage controlled oscillator to around the lock frequency, thereby shortening the lock time. The fractional frequency division method decouples the relation between the frequency resolution of the phase-locked loop and the reference frequency, so that a higher reference frequency can be selected, a larger loop bandwidth can be designed, the locking time is shortened, but the quantization noise suppression capability of the fractional frequency divider by the large bandwidth is insufficient, and the phase noise of the phase-locked loop is seriously deteriorated. The above fast locking technique requires the addition of additional auxiliary circuitry, increasing the power consumption and complexity of the phase locked loop system. In view of the above, there are difficulties and challenges in implementing a millimeter wave phase lo