CN-121984496-A - Sampling circuit and chip for high-speed interface data

CN121984496ACN 121984496 ACN121984496 ACN 121984496ACN-121984496-A

Abstract

The application provides a sampling circuit and a chip of high-speed interface data, wherein a phase-locked loop outputs a first clock signal and a frequency-doubled second clock signal based on a received reference clock signal, a logic processing module carries out multi-stage trigger sampling on the first clock signal according to the second clock signal to obtain a target clock signal, carries out multi-stage trigger sampling on a received data signal based on the target clock signal, so that the target clock signal is sampled at a designated position of the data signal, the problem of error code caused by overlarge phase difference between the clock signal and the data signal can be effectively avoided, better sampling effect and lower error rate can be obtained during high-speed data transmission, and meanwhile, a sampling clock and a control clock for parallel-serial conversion can be cooperatively adjusted in phase, thereby compensating time sequence deviation in a sampling path and an output path, and ensuring that the high-speed interface can still realize stable and reliable parallel data sampling and serial output under different speed modes.

Inventors

XIE JING
MAO ZHIFENG
SHENG BIN
Gou fei

Assignees

格兰菲智能科技股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260120

Claims (10)

1. A sampling circuit for high-speed interface data, comprising: The phase-locked loop is used for processing the received reference clock signal and outputting a reference clock signal, wherein the reference clock signal comprises a first clock signal and a second clock signal, and the second clock signal is a frequency multiplication signal of the first clock signal; The logic processing module is used for carrying out multi-stage trigger sampling on the first clock signal according to the second clock signal to obtain a target clock signal, wherein the frequency of the target clock signal is the same as that of the first clock signal and the target clock signal has preset phase offset; the trigger module is used for carrying out multi-stage trigger sampling on the received data signals according to the target clock signals to obtain target data signals; And the parallel-serial conversion module is used for receiving the target data signal according to the target clock signal and outputting the target data signal according to a first control signal in a serial mode, wherein the first control signal is an inverse signal of the second clock signal.
2. The sampling circuit of claim 1, wherein the reference clock signal further comprises a third clock signal, the third clock signal comprising at least one sub-clock signal; The parallel-serial conversion module is further configured to receive the target data signal according to the target clock signal, and output the target data signal in a serial manner according to the first control signal and each sub-clock signal.
3. The sampling circuit of claim 1, wherein the trigger module comprises a first trigger and a second trigger; The data input end of the first trigger is connected with a received data signal, the clock input end of the first trigger is connected with a received reference clock signal, and the output end of the first trigger is connected with the data input end of the second trigger; And the clock input end of the second trigger is connected with the target clock signal, and the output end of the second trigger is connected with the parallel-serial conversion module.
4. The sampling circuit of claim 1, wherein the logic processing module comprises a third flip-flop, a fourth flip-flop, a first inverter, and a second inverter; The second clock signal is connected with the input end of the first inverter, and the output end of the first inverter is respectively connected with the clock input end of the third trigger and the input end of the second inverter; The data input end of the third trigger is connected with the first clock signal, and the output end of the third trigger is connected with the data input end of the fourth trigger; The output end of the second inverter is connected with the clock input end of the fourth trigger; and the output end of the fourth trigger is respectively connected with the trigger module and the parallel-serial conversion module.
5. The sampling circuit of claim 1, wherein the logic processing module comprises a third flip-flop, a fourth flip-flop, a first inverter, a second inverter, a third inverter, and a fourth inverter; The second clock signal is connected with the input end of the first inverter, and the output end of the first inverter is respectively connected with the clock input end of the third trigger and the input end of the second inverter; The data input end of the third trigger is connected with the first clock signal, the output end of the third trigger is connected with the input end of the third inverter, and the output end of the third inverter is connected with the data input end of the fourth trigger; The output end of the second inverter is connected with the clock input end of the fourth trigger; The output end of the fourth trigger is connected with the input end of the fourth inverter, and the output end of the fourth inverter is respectively connected with the trigger module and the parallel-serial conversion module.
6. The sampling circuit of claim 1, wherein the phase-locked loop comprises: a first conversion unit for processing the reference clock signal into a fourth clock signal; The adjusting unit is used for generating a control signal according to the phase deviation of the fourth clock signal and the feedback clock signal, and adjusting the oscillation frequency according to the control signal to obtain a fifth clock signal; The first frequency divider is used for dividing the frequency of the fifth clock signal to obtain the reference clock signal; And the second conversion unit is used for processing the first clock signal in the reference clock signals into a feedback clock signal.
7. The sampling circuit of claim 6, wherein: The first conversion unit comprises a first logic gate for shaping the reference clock signal to a fourth clock signal; the second conversion unit comprises a second logic gate for shaping the first clock signal into a feedback clock signal.
8. The sampling circuit of claim 6, wherein: The first conversion unit comprises a first level conversion unit and a second frequency divider, wherein the first level conversion unit is used for converting the voltage of the reference clock signal into a target voltage domain; The second conversion unit comprises a second level conversion unit and a third frequency divider, wherein the second level conversion unit is used for converting the voltage of the first clock signal into a target voltage domain, and the third frequency divider is used for dividing the first clock signal in the target voltage domain into a feedback clock signal.
9. The sampling circuit of claim 1, wherein: the logic processing module is further used for respectively carrying out delay processing on the target clock signal and the first control signal; the trigger module is also used for carrying out delay processing in the process of carrying out multistage trigger sampling on the received data signals to obtain target data signals; The parallel-serial conversion module is further configured to receive the target data signal according to the target clock signal after delay processing, and output the target data signal according to the first control signal after delay processing in a serial manner.
10. A chip, characterized by comprising the high-speed interface data sampling circuit according to any one of claims 1-9.

Description

Sampling circuit and chip for high-speed interface data Technical Field The present application relates to the field of digital signal processing technologies, and in particular, to a sampling circuit and a chip for high-speed interface data. Background With the advent of the 5G and artificial intelligence era, there has been a growing need for high-speed, efficient, low-power data transmission solutions, both in the fields of data centers, communication networks, consumer electronics, industrial automation, etc. Taking video signal transmission as an example, as the resolution of the screen display increases gradually, the requirement for transmission rate increases continuously, and the requirement for high-speed serial data interfaces increases. The high-speed interface circuit relates to a complex digital-analog hybrid circuit design, and along with the improvement of the transmission rate, how to correctly sample the high-speed data sent by the digital part according to different rate requirements and complete the parallel-serial conversion of the high-speed data becomes a great difficulty. In the prior art, the high-speed data sampling is generally realized by adjusting the phase of a sampling clock signal, on one hand, by adjusting the delay of a clock signal path to meet the requirements of the setup time (setup time) and the hold time (hold time) of a sampling trigger, thereby completing the correct sampling of the high-speed data, and on the other hand, the sampled parallel data signal is matched with a corresponding clock signal and is input into a parallel-serial conversion circuit, so that the serial output of the high-speed data is realized. In order to ensure that the multi-bit parallel data can be correctly sampled, the phase relationship between the clock signal (CLK) and the data signal (data) needs to be tightly controlled. Along with the continuous increase of the transmission rate, the frequency of a clock signal is higher and higher, a phase window between the clock signal and a data signal is obviously narrowed, any tiny mismatch in a clock path and a data path can cause that the phase difference of the clock signal and the data path is difficult to control accurately, and when the phase deviation is overlarge, sampling errors are easy to occur, so that the error rate of a link is further deteriorated. In a multi-rate or combined (comb) interface sampling system, the sampling clock is typically generated by a Phase Locked Loop (PLL) to a plurality of clock signals of different frequencies or phases, which is more complex in structure, making it more difficult to perform stable and reliable correct sampling and parallel-to-serial conversion of parallel data in different rate modes. Disclosure of Invention The application aims to solve the technical problem of providing a sampling circuit and a chip of high-speed interface data, so as to solve the problem that the bit error rate is high during parallel-serial conversion because the phase between a clock signal and a data signal is difficult to control accurately in the traditional technology. In a first aspect, the present application provides a sampling circuit for high-speed interface data, including: The phase-locked loop is used for processing the received reference clock signal and outputting a reference clock signal, wherein the reference clock signal comprises a first clock signal and a second clock signal, and the second clock signal is a frequency multiplication signal of the first clock signal; The logic processing module is used for carrying out multi-stage trigger sampling on the first clock signal according to the second clock signal to obtain a target clock signal, wherein the frequency of the target clock signal is the same as that of the first clock signal and the target clock signal has preset phase offset; the trigger module is used for carrying out multi-stage trigger sampling on the received data signals according to the target clock signals to obtain target data signals; And the parallel-serial conversion module is used for receiving the target data signal according to the target clock signal and outputting the target data signal according to a first control signal in a serial mode, wherein the first control signal is an inverse signal of the second clock signal. In one embodiment, the reference clock signal further comprises a third clock signal, the third clock signal comprising at least one sub-clock signal; The parallel-serial conversion module is further configured to receive the target data signal according to the target clock signal, and output the target data signal in a serial manner according to the first control signal and each sub-clock signal. In one embodiment, the trigger module includes a first trigger and a second trigger; The data input end of the first trigger is connected with a received data signal, the clock input end of the first trigger is connected with a received reference clock signal, and