Search

CN-121984497-A - Decimal frequency division phase-locked loop for FMCW radar

CN121984497ACN 121984497 ACN121984497 ACN 121984497ACN-121984497-A

Abstract

The invention relates to a fractional frequency division phase-locked loop for an FMCW radar, which comprises a frequency discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator, a multi-mode frequency divider, a delta-sigma modulator, a chirp signal generation module and a linearity calibration module, wherein when the fractional frequency division phase-locked loop is in a closed loop acquisition mode, the chirp signal generation module acquires control voltage time sequence data of the voltage-controlled oscillator in a complete chirp period, and when the fractional frequency division phase-locked loop is in an open loop drive mode, the chirp signal generation module generates an analog voltage signal according to the control voltage time sequence data and drives the voltage-controlled oscillator to output the chirp signal. The invention solves the problems of poor VCO tuning linearity, performance drift at extreme temperature, quantization noise leakage, insufficient multi-target interference adaptation, low frequency modulation response speed and the like in the prior art, and simultaneously improves the ranging precision of the FMCW radar, in particular to improve the short-range ranging performance and the high-speed target detection capability.

Inventors

  • WANG JIAWEI
  • XIAO SHIMAO

Assignees

  • 南京中科微电子有限公司

Dates

Publication Date
20260505
Application Date
20260112

Claims (10)

  1. 1. The decimal frequency division phase-locked loop for the FMCW radar is characterized by comprising a phase frequency detector (1), a charge pump (2), a low-pass filter (3), a voltage-controlled oscillator (4), a multimode frequency divider (5) and a delta-sigma modulator (6), a chirp signal generation module (7) and a linearity calibration module (8); The output end of the phase frequency detector (1) is connected with the input end of the charge pump (2), the output end of the charge pump (2) is connected with the input end of the low-pass filter (3), the output end of the low-pass filter (3) is connected with the input end of the chirp signal generation module (7), the output end of the chirp signal generation module (7) is connected with the input end of the voltage-controlled oscillator (4), the output end of the voltage-controlled oscillator (4) is connected with the linearity calibration module (8) and one input end of the multi-mode frequency divider (5), the other input end of the multi-mode frequency divider (5) is connected with the delta-sigma modulator (6), and the output end of the multi-mode frequency divider (5) is connected with the input end of the phase frequency detector (1); When the fractional frequency phase-locked loop is in a closed loop acquisition mode, the chirp signal generation module (7) acquires control voltage time sequence data of the voltage-controlled oscillator (4) in a complete chirp period; When the fractional frequency phase-locked loop is in an open-loop driving mode, the chirp signal generation module (7) generates an analog voltage signal according to control voltage time sequence data, and drives the voltage-controlled oscillator (4) to output the chirp signal.
  2. 2. The fractional-n phase-locked loop for FMCW radar according to claim 1, wherein the chirp signal generation module (7) includes a mode switching unit (71), an analog-to-digital conversion unit (72), a storage unit (73) and a digital-to-analog conversion unit (74), the mode switching unit (71) is connected to an output of the low-pass filter (3), an input of the analog-to-digital conversion unit (72) and an output of the digital-to-analog conversion unit (74), an output of the analog-to-digital conversion unit (72) is connected to an input of the storage unit (73), and an output of the storage unit (73) is connected to an input of the digital-to-analog conversion unit (74).
  3. 3. The fractional-n phase-locked loop for FMCW radar according to claim 2, characterized in that the mode switching unit (71) is capable of connecting the output of the low-pass filter (3) with the input of the voltage-controlled oscillator (4) and with the input of an analog-to-digital conversion unit (72) when the fractional-n phase-locked loop is in closed loop acquisition mode; the output of the low-pass filter (3) can be connected to the input of the voltage-controlled oscillator (4) and to the output of the digital-to-analog conversion unit (74) when the fractional-divider phase-locked loop is in an open-loop drive mode.
  4. 4. The fractional pll for FMCW radar according to claim 1, characterized in that the linearity calibration module (8) comprises a linearity detection module (81), a calibration voltage generation module (82), a feedback control module (83), an input of the linearity detection module (81) being connected to a voltage controlled oscillator (4), an output of the linearity detection module (81) being connected to an input of the calibration voltage generation module (82), an output of the calibration voltage generation module (82) being connected to an input of the feedback control module (83), an output of the feedback control module (83) being connected to the voltage controlled oscillator (4); the linearity detection module (81) converts the frequency modulation signal output by the voltage-controlled oscillator (4) into a corresponding voltage signal, compares the voltage signal with a preset ideal linear voltage reference curve and outputs a linearity error signal; -the calibration voltage generation module (82) converting the linearity error signal into an analog calibration voltage; The feedback control module (83) is configured to compensate the analog calibration voltage when the voltage controlled oscillator (4) is at a preset temperature.
  5. 5. The fractional-n phase-locked loop for an FMCW radar of claim 1, wherein the charge pump employs a current steering charge pump topology.
  6. 6. Fractional frequency phase locked loop for FMCW radar according to claim 1 characterized in that the low pass filter (3) employs a passive third order RC topology.
  7. 7. The fractional-n pll for FMCW radar of claim 1, wherein the voltage-controlled oscillator (4) includes a current source I1, a MOS stack, a resistor R1, a capacitor C1, an inductor L1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a coarse tuning capacitor stack, a fine tuning capacitor stack; The positive pole of the current source I1 is connected with the working voltage VDD, the negative pole of the current source I1 is connected with one end of the MOS tube group, the other end of the MOS tube group is grounded, the grid electrode of the MOS tube group is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the capacitor C1 and the grid electrode of the first MOS tube M1, the other end of the capacitor C1 is grounded, The source electrode of the first MOS tube M1 is grounded, the drain electrode of the first MOS tube M1 is connected with the source electrode of the second MOS tube M2 and the source electrode of the third MOS tube M3, the grid electrode of the second MOS tube M2 is connected with the drain electrode of the third MOS tube M3, one end of a coarse adjustment capacitor group, one end of a fine adjustment capacitor group, one end of an ultrafine adjustment capacitor group and one end of an inductor L1, and the grid electrode of the third MOS tube M3 is connected with the drain electrode of the second MOS tube M2, and the drain electrode of the second MOS tube M2 is connected with the other end of the coarse adjustment capacitor group, the other end of the fine adjustment capacitor group, the other end of the ultrafine adjustment capacitor group and the other end of the inductor L1.
  8. 8. The fractional-N phase-locked loop for FMCW radar of claim 7 wherein, The coarse tuning capacitor group comprises 2 groups of MOS varactors which are connected in parallel and have slightly larger capacitance values; The fine-tuning capacitor group comprises 3 MOS varactors with medium capacitance values and is used for finely calibrating the working frequency band to the target frequency band; the superfine capacitance adjusting group adopts a low-noise MOS varactor.
  9. 9. The fractional-n pll for FMCW radar of claim 1, wherein the multi-modulus divider employs a synchronous divide architecture supporting integer divide ratio switching in the range of 2 N ~2 N+1 "1.
  10. 10. The fractional-n phase-locked loop for FMCW radar of claim 1, wherein the delta-sigma modulator employs a 3-order sp-marsh 111 topology.

Description

Decimal frequency division phase-locked loop for FMCW radar Technical Field The invention relates to the technical field of radio frequency integrated circuit design, in particular to a decimal frequency division phase-locked loop for an FMCW radar. Background The FMCW radar is widely applied to the fields of vehicle ranging, industrial detection, security monitoring and the like by virtue of the advantages of simple structure, high ranging precision, strong anti-interference capability and the like. In an FMCW radar system, the quality of a linear frequency modulation signal output by a local oscillation module directly determines the ranging accuracy of a radar, the larger the linearity error of the frequency modulation signal is, the more serious the difference frequency signal distortion between a radar echo and the local oscillation signal is, so that the ranging error is increased, and the problem is more remarkable especially in a short-distance ranging scene. The decimal frequency division PLL has the characteristics of high frequency resolution and wide output frequency band, and becomes a core choice of the FMCW radar local oscillation module. However, existing fractional PLL have the following technical pain points: 1. The tuning linearity of the voltage-controlled oscillator (VCO) is insufficient, the traditional VCO mostly adopts a single-stage or two-stage capacitor tuning structure, and the capacitor-voltage (C-V) nonlinear characteristic of a varactor is easy to cause larger tuning linearity error near the first frequency band, so that the requirement of short-distance high-precision ranging cannot be met; 2. The extreme environment adaptability is poor, namely, under the wide temperature working scene of minus 40 ℃ to 125 ℃, the capacitance value of a Low Pass Filter (LPF) and the output current of a Charge Pump (CP) drift along with the temperature, so that the stability of a PLL loop is reduced, and the linearity of VCO frequency modulation is further deteriorated; 3. Quantization noise suppression is insufficient, namely quantization noise generated by the delta-sigma modulator is easy to leak in the frequency band of 80-100 MHz and cannot be completely suppressed by the traditional LPF, so that the output signal stray of the PLL is increased, and the anti-interference capability of the radar is affected; 4. the traditional decimal frequency division PLL adopts a closed loop regulation mechanism, the locking delay usually reaches a few microseconds, the frequency modulation slope is limited, and the requirement of high-speed target detection on a quick chirp signal cannot be met; therefore, developing a fractional PLL that has high linearity, wide temperature stability, low noise characteristics, and fast frequency modulation capability, and that adapts to the multi-scenario requirements of FMCW radars, is an urgent need in the current rf integrated circuit design field. Disclosure of Invention The invention aims to overcome the defects of the traditional fractional frequency-division phase-locked loop in the application of an FMCW radar, and provides the fractional frequency-division phase-locked loop capable of generating a quick and high-linearity chirp signal, which solves the problems of poor tuning linearity of a VCO, performance drift at extreme temperature, quantization noise leakage, insufficient multi-target interference adaptation, low frequency modulation response speed and the like in the prior art, and improves the ranging precision (especially improves the short-range ranging performance) and the high-speed target detection capability of the FMCW radar. The technical scheme of the invention is that the fractional frequency division phase-locked loop for the FMCW radar comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a multi-mode frequency divider, a delta-sigma modulator, a chirp signal generation module and a linearity calibration module; The output end of the phase frequency detector is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the low-pass filter, the output end of the low-pass filter is connected with the input end of the chirp signal generation module, the output end of the chirp signal generation module is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the linearity calibration module and one input end of the multi-mode frequency divider, the other input end of the multi-mode frequency divider is connected with the delta-sigma modulator, and the output end of the multi-mode frequency divider is connected with the input end of the phase frequency detector; when the fractional frequency pll is in a closed loop acquisition mode, the chirp signal generation module acquires control voltage time sequence data of a voltage-controlled oscillator in a comple