Search

CN-121984498-A - PLL loop bandwidth adjusting circuit, control method and circuit board

CN121984498ACN 121984498 ACN121984498 ACN 121984498ACN-121984498-A

Abstract

The PLL loop bandwidth adjusting circuit, the control method and the circuit board comprise a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage-controlled oscillator, wherein the input end of the phase frequency detector is connected with a reference signal, the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter, and the second output end of the phase frequency detector is connected with the second input end of the adjustable voltage-controlled oscillator through the phase-locked loop proportional path module.

Inventors

  • ZHANG MINGKANG
  • ZHANG ZEHAO
  • MA RUI

Assignees

  • 成都澳世芯科技有限责任公司

Dates

Publication Date
20260505
Application Date
20231221

Claims (8)

  1. 1. The PLL loop bandwidth adjusting circuit is characterized by comprising a phase frequency detector (10), a charge sharing filter (20), a phase-locked loop proportional path module (30) and an adjustable voltage controlled oscillator (40); the input end of the phase frequency detector (10) is connected with a reference signal; the first output end of the phase frequency detector (10) is connected with the first input end of the adjustable voltage-controlled oscillator (40) through the charge sharing filter (20); and a second output end of the phase frequency detector (10) is connected with a second input end of the adjustable voltage controlled oscillator (40) through a phase-locked loop proportional path module (30).
  2. 2. The PLL loop bandwidth adjustment circuit of claim 1, wherein the charge sharing filter (20) comprises an integrating path module (201) and a low pass filtering module (202); The first output end of the phase frequency detector (10) is connected with the first input end of the adjustable voltage-controlled oscillator (40) through an integrating path module (201) and a low-pass filtering module (202).
  3. 3. The PLL loop bandwidth adjustment circuit of claim 1, wherein the adjustable voltage controlled oscillator (40) is a variable VCO switched capacitor array.
  4. 4. The PLL loop bandwidth adjustment circuit of claim 2, wherein the variable VCO switched capacitor array comprises a switching circuit module (401) and a VCO circuit module (402), the VCO circuit module (402) being electrically disconnected from or connected to the charge sharing filter (20) and the phase locked loop proportional path module (30) by the switching circuit module (401).
  5. 5. The PLL loop bandwidth adjustment circuit of claim 4 wherein said VCO circuit module (402) is configured to include a first variable capacitor C1, a second variable capacitor C2, a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, an inductor L1, and a variable capacitor array CV; The first MOS tube Q1 and the second MOS tube Q2 form a first cross-coupling negative resistance, and the third MOS tube Q3 and the fourth MOS tube Q4 form a second cross-coupling negative resistance; The first end of the first cross-coupling negative resistance is connected with the second end of the first cross-coupling negative resistance in parallel and then connected with the voltage end VDD; The third end of the first cross-coupled negative resistance is respectively connected with the first end of the inductor L1, the first end of the first variable capacitor C1, the first end of the variable capacitor array CV and the first end of the second cross-coupled negative resistance; The fourth end of the first cross-coupling negative resistance is respectively connected with the second end of the inductor L1, the first end of the second variable capacitor C2, the second end of the variable capacitor array CV and the second end of the second cross-coupling negative resistance, and the third end of the second cross-coupling negative resistance is connected with the fourth end of the first cross-coupling negative resistance in parallel and then grounded; the second end of the first variable capacitor C1 is connected with the second end of the second variable capacitor C2; The switching circuit module (401) is connected to the variable capacitance array CV.
  6. 6. A PLL loop bandwidth adjustment circuit according to claim 1, characterized in that the feedback signal terminal of the adjustable voltage controlled oscillator (40) is connected to the feedback signal input terminal of the phase frequency detector (10) via a frequency divider (50).
  7. 7. A control method of the PLL loop bandwidth adjusting circuit, characterized in that the PLL loop bandwidth adjusting circuit employs the PLL loop bandwidth adjusting circuit according to any one of claims 1 to 6, the control method comprising: and the proportional path gain value in the proportional path module of the phase-locked loop is adjusted by changing the output frequency of the adjustable voltage-controlled oscillator, so that the modulation of the PLL loop bandwidth is realized.
  8. 8. A circuit board of a PLL loop bandwidth adjustment circuit, comprising the PLL loop bandwidth adjustment circuit of any one of claims 1 to 6, and a substrate carrying the PLL loop bandwidth adjustment circuit.

Description

PLL loop bandwidth adjusting circuit, control method and circuit board Technical Field The invention relates to the technical field of phase-locked sources, in particular to a PLL loop bandwidth adjusting circuit, a control method and a circuit board. Background Referring to fig. 1 and 2, PLL (Phase Locked Loop) is a phase-locked loop or phase-locked loop for unifying and integrating clock signals to make high-frequency devices work normally, and the PLL loop bandwidth is equal to the integral of its closed loop frequency response, which reflects the noise suppression effect of the loop, and the smaller the noise bandwidth, the narrower the loop and the stronger the input noise suppression capability of the loop. In addition, the noise bandwidth is also related to the loop gain K, damping coefficient, undamped oscillation frequency, etc. From the above, the conventional PLL loop bandwidth control is limited by "noise-power consumption", and a higher PLL loop bandwidth means a lower lock time, and at the same time, the improvement of the PLL bandwidth reduces the suppression capability of the loop system to in-band noise, thereby introducing more clock jitter in the output clock signal. In general, in order to improve the loop bandwidth without affecting the noise performance, additional noise processing means are required to be introduced, including increasing the reference clock frequency, introducing an auxiliary loop, increasing the charge pump current, etc., but all of the above methods are contrary to low power designs, making the "noise-power" constraint difficult to solve. Disclosure of Invention In view of the above, there is a need to provide a PLL loop bandwidth adjusting circuit, a control method, and a circuit board with high flexibility and low power consumption. The invention provides a PLL loop bandwidth adjusting circuit, which comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage controlled oscillator; The input end of the phase frequency detector is connected with a reference signal; The first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter; And a second output end of the phase frequency detector is connected with a second input end of the adjustable voltage-controlled oscillator through a phase-locked loop proportional path module. Optionally, the charge sharing filter comprises an integrating path module and a low-pass filtering module; the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the integrating path module and the low-pass filter module. Optionally, the adjustable voltage controlled oscillator is a variable VCO switched capacitor array. Optionally, the variable VCO switched capacitor array includes a switch circuit module and a VCO circuit module electrically disconnected or connected with the charge sharing filter and the phase locked loop proportional path module through the switch circuit module. Optionally, the VCO circuit module has a structure comprising a first variable capacitor C1, a second variable capacitor C2, a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3, a fourth MOS tube Q4, an inductor L1 and a variable capacitor array CV; The first MOS tube Q1 and the second MOS tube Q2 form a first cross-coupling negative resistance, and the third MOS tube Q3 and the fourth MOS tube Q4 form a second cross-coupling negative resistance; The first end of the first cross-coupling negative resistance is connected with the second end of the first cross-coupling negative resistance in parallel and then connected with the voltage end VDD; The third end of the first cross-coupled negative resistance is respectively connected with the first end of the inductor L1, the first end of the first variable capacitor C1, the first end of the variable capacitor array CV and the first end of the second cross-coupled negative resistance; The fourth end of the first cross-coupling negative resistance is respectively connected with the second end of the inductor L1, the first end of the second variable capacitor C2, the second end of the variable capacitor array CV and the second end of the second cross-coupling negative resistance, and the third end of the second cross-coupling negative resistance is connected with the fourth end of the first cross-coupling negative resistance in parallel and then grounded; the second end of the first variable capacitor C1 is connected with the second end of the second variable capacitor C2; The switching circuit module 401 is connected to the variable capacitance array CV. Optionally, the feedback signal end of the adjustable voltage controlled oscillator is connected with the feedback signal input end of the phase frequency detector through a frequency divider. T