CN-121984499-A - Full-digital fractional frequency-division phase-locked loop based on high-level synthesis and implementation method thereof

CN121984499ACN 121984499 ACN121984499 ACN 121984499ACN-121984499-A

Abstract

The application discloses a full digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, wherein the full digital fractional frequency division phase-locked loop comprises a time-to-digital converter, a register-based transmission stage and a feedback frequency divider, wherein the time-to-digital converter is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by the feedback frequency divider; the digital loop filter is realized based on high-level synthesis and is used for outputting a frequency control word according to a phase error signal, the digital control oscillator is realized based on an IP core and is used for outputting a digital sine wave signal according to the frequency control word, and the feedback frequency divider is realized based on high-level synthesis and is used for outputting a feedback clock signal according to the digital sine wave signal. The application strategically combines high-level synthesis with register transmission stage design by strategically dividing the modules in the all-digital phase-locked loop, realizes the all-digital phase-locked loop which has high performance, high efficiency and stable locking, and can be widely applied to the technical field of digital circuit design.

Inventors

MENG HUIHUI
LIN QINGGANG
WENG JIAJIE

Assignees

广州赛恩科学仪器有限公司

Dates

Publication Date: 20260505
Application Date: 20251212

Claims (10)

1. An all-digital fractional-n phase-locked loop based on high-level synthesis, comprising: The time-digital converter is realized based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; The input end of the digital loop filter is connected with the output end of the time-digital converter, and is used for outputting a frequency control word according to the phase error signal based on high-level comprehensive implementation; The input end of the numerical control oscillator is connected with the output end of the digital loop filter, is realized based on an IP core and is used for outputting a digital sine wave signal according to the frequency control word; The input end of the feedback frequency divider is connected with the output end of the numerical control oscillator, the output end of the feedback frequency divider is connected with the input end of the time-digital converter, and the feedback frequency divider is used for outputting the feedback clock signal according to the digital sine wave signal based on high-level comprehensive implementation.
2. The all-digital fractional-n phase-locked loop of claim 1, further comprising: The input end of the modulator is connected with the output end of the digital loop filter, and the modulator is also connected with the feedback frequency divider and is used for outputting a digital sequence according to the frequency control word, and the digital sequence is used for controlling the frequency division ratio of the feedback frequency divider.
3. A method for implementing an all-digital fractional-n phase-locked loop based on high-level synthesis, implemented by an all-digital fractional-n phase-locked loop based on high-level synthesis as claimed in any one of claims 1 to 2, comprising the steps of: Outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider through a time-to-digital converter; outputting a frequency control word according to the phase error signal through a digital loop filter; outputting a digital sine wave signal according to the frequency control word through a numerical control oscillator; Outputting, by the feedback frequency divider, the feedback clock signal according to the digital sine wave signal; Wherein the time-to-digital converter is implemented based on a register transfer stage, the digital loop filter and the feedback divider are implemented based on high-level synthesis, and the digitally controlled oscillator is implemented based on an IP core.
4. A method according to claim 3, wherein the outputting, by the time-to-digital converter, the phase error signal based on the externally input reference clock signal and the feedback clock signal input by the feedback divider, comprises: Receiving, by the time-to-digital converter, the reference clock signal, the feedback clock signal, and a first system clock signal; And calculating the phase difference between the reference clock signal and the feedback clock signal according to the first system clock signal, and outputting the phase error signal.
5. A method according to claim 3, wherein said outputting, by a digital loop filter, a frequency control word based on said phase error signal, comprises: Receiving the phase error signal through the digital loop filter; And performing proportional and integral operation on the phase error signal, and outputting the frequency control word.
6. The method according to claim 5, wherein said performing a proportional and integral operation on said phase error signal outputs said frequency control word, comprising: Calculating a proportional term and an integral term according to the phase error signal; Performing integral saturation judgment on the integral term, and further clamping or updating the integral term according to an integral saturation judgment result; calculating a control increment according to the proportional term and the clamped or updated integral term; calculating the output value of the frequency control word according to the control increment; determining a maximum value and a minimum value of the frequency control word; And carrying out output saturation judgment on the output value according to the maximum value of the frequency control word and the minimum value of the frequency control word, and outputting the output value, the maximum value of the frequency control word or the minimum value of the frequency control word according to an output saturation judgment result.
7. The method according to claim 6, wherein the performing output saturation determination on the output value according to the frequency control word maximum value and the frequency control word minimum value, and further outputting the output value, the frequency control word maximum value, or the frequency control word minimum value according to an output saturation determination structure, specifically comprises: Outputting the output value when the output value is larger than the minimum value of the frequency control word and smaller than the maximum value of the frequency control word; When the output value is smaller than the minimum value of the frequency control word, outputting the minimum value of the frequency control word; And outputting the maximum value of the frequency control word when the output value is larger than the maximum value of the frequency control word.
8. A method according to claim 3, wherein said outputting, by a digitally controlled oscillator, a digital sine wave signal in accordance with said frequency control word, comprises: receiving, by the numerically controlled oscillator, the frequency control word and a second system clock signal; converting the frequency control word into a phase gain; Accumulating the phase gain according to the second system clock signal by a phase accumulator in the numerical control oscillator to obtain an accumulation result; And outputting the digital sine wave signal according to the sine and cosine lookup table and the accumulation result.
9. A method according to claim 3, wherein said outputting, by said feedback divider, said feedback clock signal from said digital sine wave signal, comprises: receiving the digital sine wave signal and a target frequency division coefficient through the feedback frequency divider; performing sign bit inversion on the digital sine wave signal to obtain a square wave signal; dividing the square wave signal according to the target frequency division coefficient to obtain the feedback clock signal; The feedback clock signal is output to the time-to-digital converter.
10. A method according to claim 3, characterized in that the method further comprises: And outputting a digital sequence by a modulator according to the frequency control word, wherein the digital sequence is used for controlling the frequency division ratio of the feedback frequency divider.

Description

Full-digital fractional frequency-division phase-locked loop based on high-level synthesis and implementation method thereof Technical Field The application relates to the technical field of digital circuit design, in particular to an all-digital fractional frequency-division phase-locked loop based on high-level synthesis and an implementation method thereof. Background Phase locked loops (PhaseLockedLoop, PLL) are indispensable core modules in modern communication, computing and signal processing systems, whose main functions are to achieve frequency synthesis and clock synchronization. The conventional analog phase-locked loop (APLL) is mainly implemented by analog circuits. Analog circuits, however, face significant challenges in modern deep sub-micron CMOS processes, in that, first, analog circuits are highly sensitive to process, voltage and temperature (PVT) variations, have poor stability, and are not robust enough. Second, analog designs (e.g., high voltage VCOs) are themselves very complex, have long design cycles, and are difficult to migrate between different process nodes. In addition, passive components such as large capacitors required for analog filters occupy a large amount of chip area, and are difficult to be compatible with highly integrated digital systems-on-chip (SoC). With the rapid increase of the integration level of digital circuits, the traditional analog phase-locked loop (APLL) has become a bottleneck for digital SoC integration. To overcome the above-mentioned drawbacks of the conventional analog phase-locked loop (APLL), an all-digital phase-locked loop has been developed. The all-digital phase-locked loop uses a digital module to replace all analog modules, and has the remarkable advantages of insensitivity to process, voltage and temperature (PVT), easiness in integration, strong portability, easiness in scaling along with the process and the like. However, the existing design method of the all-digital phase-locked loop has a clear technical blank that the implementation method of the pure Register Transfer Level (RTL) has the defects of high algorithm iteration and maintenance cost and low development efficiency although the function is feasible, and the implementation method of the pure high-level synthesis (HLS) has the defect of functional failure on a key time sequence module (such as TDC) required by the all-digital phase-locked loop although the development efficiency is high. In addition, most phase-locked loops in the industry are only manufactured based on small integrated chips, the precision and flexibility of the phase-locked loops are far less than those of FPGA development systems based on High Level Synthesis (HLS), and the related technologies of the high-precision phase-locked loop technology are very few. Disclosure of Invention In order to solve the technical problems, the application aims to provide a high-performance, high-efficiency and stable-locking full-digital fractional-N phase-locked loop based on high-level synthesis and an implementation method thereof. To achieve the above objective, an aspect of the embodiments of the present application provides an all-digital fractional-n pll based on high-level synthesis, including: The time-digital converter is realized based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; The input end of the digital loop filter is connected with the output end of the time-digital converter, and is used for outputting a frequency control word according to the phase error signal based on high-level comprehensive implementation; The input end of the numerical control oscillator is connected with the output end of the digital loop filter, is realized based on an IP core and is used for outputting a digital sine wave signal according to the frequency control word; The input end of the feedback frequency divider is connected with the output end of the numerical control oscillator, the output end of the feedback frequency divider is connected with the input end of the time-digital converter, and the feedback frequency divider is used for outputting the feedback clock signal according to the digital sine wave signal based on high-level comprehensive implementation. In some embodiments, the all-digital fractional-n phase-locked loop further comprises: The input end of the modulator is connected with the output end of the digital loop filter, and the modulator is also connected with the feedback frequency divider and is used for outputting a digital sequence according to the frequency control word, and the digital sequence is used for controlling the frequency division ratio of the feedback frequency divider. In order to achieve the above objective, another aspect of the embodiments of the present application provides a method for implementing an all-digital fractional-n pll