CN-121984500-A - Sampling moment mismatch background calibration algorithm based on two-stage difference value

CN121984500ACN 121984500 ACN121984500 ACN 121984500ACN-121984500-A

Abstract

The invention discloses a sampling time mismatch background calibration algorithm based on two-stage difference values, which consists of a data buffer module, a first-order differential module, an error correction module, a 1:4 data distributor module, a two-stage difference value operation module, a matrix operation module and a self-adaptive iteration module, the calibration algorithm selects the first channel in the multi-channel time-interleaved ADC as a reference channel to calibrate the rest channels, simplifies a first-order differential circuit, and rapidly obtains a differential approximation value by a mean value obtaining method.

Inventors

YUAN YONGBIN
LIAO YONG
LIANG JIANGSHAN
BAI JINSONG

Assignees

上海源斌电子科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251217

Claims (5)

1. The utility model provides a sampling moment mismatch background calibration algorithm based on two-stage difference, its characterized in that, this algorithm is applicable to the time interleaving ADC design calibration of arbitrary passageway, and this calibration algorithm selects the first passageway in multichannel time interleaving ADC to be the reference channel and calibrates other passageways, and the algorithm is whole by data buffer module, first order differential module, error correction module, 1:4 data distributor module, two-stage difference operation module, matrix operation module, self-adaptation iteration module constitution, wherein: The data caching module inputs sampling values of the multi-channel time interleaving ADC and caches the sampling values; The first-order differential module is used for inputting the sampling value stored in the data buffer module, and obtaining a differential value of the sampling value by averaging the previous sampling value and the next sampling value of the sampling value, wherein the differential value is used as the output of the first-order differential module; The error correction module is used for obtaining an output value of the error correction module by subtracting the product of the sampling value stored in the data buffer module, the output value of the first-order differential module and the adaptive iteration, wherein the output value is a correction result; The input of the 1:4 data distributor module is an output value of the error correction module, and the data distributor module divides the input value into four paths of output values; The two-stage difference value operation module inputs four paths of output values of the 1:4 data distributor module, the two-stage difference value operation module subtracts two paths of adjacent values, takes absolute values of the subtracted values, averages the subtracted values to obtain four paths of expected values, and subtracts the obtained adjacent expected values to obtain three output values of the two-stage difference value operation module; the matrix operation module inputs the output values of the two-stage difference operation module, and the matrix operation module obtains sampling time deviation as the output value of the matrix operation module by carrying out matrix operation on the output values of the two-stage difference operation module and the set coefficient matrix; and the self-adaptive iteration module takes the matrix operation module as an output value as an input, and multiplies the input value and the set iteration step value by the self-adaptive iteration module to obtain the output value of the self-adaptive iteration module.
2. The two-stage difference value-based sampling time mismatch background calibration algorithm according to claim 1, wherein the first-order differential module obtains a differential value of a sampling value by averaging a previous sampling value and a next sampling value of the sampling value, obtains the differential value by simple averaging approximation, reduces the circuit complexity of the first-order differential module compared with a complex differential filter, and improves the speed of realizing a circuit by the algorithm.
3. The two-stage difference value-based sampling time mismatch background calibration algorithm according to claim 1, wherein the error correction module corrects the sampling value by a first-order differential approximation method, so as to eliminate errors caused by sampling time mismatch between different channels.
4. The two-stage difference-based sampling time mismatch background calibration algorithm according to claim 1, wherein the matrix operation module completes matrix operation through left-right shift and addition and subtraction operations, thereby simplifying circuit complexity.
5. The two-stage difference value-based sampling time mismatch background calibration algorithm according to claim 1, wherein the adaptive iteration module performs adaptive iteration on the sampling value through a set iteration step value, and only 2500 iterations are needed to converge to obtain a final calibration value.

Description

Sampling moment mismatch background calibration algorithm based on two-stage difference value Technical Field The invention belongs to the technical field of integrated circuits, and particularly relates to a sampling moment mismatch background calibration algorithm based on two-stage difference values. Background With the popularization and application of the internet of things and telecommunication systems, technical means are continuously innovated. It is difficult to accommodate the ever-increasing performance demands by means of conventional single channel ADC types. In order to break through the design constraint of single channel ADC on sampling rate and conversion accuracy, the university of california berkeley division in 1980 proposed a Time-interleaved analog-to-digital converter (Time-interleavedAnalog to Digital Converters, TIADC) design architecture. The time interleaving structure can multiply and improve the sampling rate of the whole TIADC under the condition of keeping the conversion precision of the single-channel ADC unchanged by a plurality of low-speed sub-ADCs in parallel interleaving and sampling, so the time interleaving structure is one of the most effective and popular technologies in the current and future high-performance ADC chip designs. However, due to the influences of layout design, deviation in chip manufacturing process and the like, different parameters are presented among all sub-ADC channels, and therefore the problem of parameter mismatch among the channels is formed, and the exertion of the integral performance of TIADC is severely limited. Background (Background) calibration techniques for mismatch of sampling moments between channels mainly include calibration algorithms based on signal correlation, difference detection and zero-crossing domain signal statistics. Although error elimination of mismatch of sampling time can be effectively realized, various defects of limited input signals, suitability for only specific channel number, low convergence speed, requirement for analog auxiliary channels and the like still exist generally. The calibration technology based on signal difference detection is derived from product calculation in signal correlation, and an adder is adopted to replace a time-varying multiplier of autocorrelation operation in design, so that the cost in terms of hardware and power consumption can be effectively reduced. According to the sampling time mismatch background calibration algorithm based on the two-stage difference value, according to the first-order Taylor approximation theory of sampling signals, the sampling time mismatch value of each channel sub-ADC can be simultaneously obtained by calculating the difference value between the adjacent channel sub-ADC outputs and combining matrix operation. Disclosure of Invention The invention provides a sampling time mismatch background calibration algorithm based on two-stage difference values. The invention provides a sampling moment mismatch background calibration algorithm based on two-stage difference values, which specifically comprises a data buffer module, a first-order differential module, an error correction module, a 1:4 data distributor module, a two-stage difference value operation module, a matrix operation module and a self-adaptive iteration module, wherein: And the data caching module inputs sampling values of the multi-channel time interleaving ADC and caches the sampling values. The first-order differential module is input into the sampling value stored in the data buffer module, and the first-order differential module obtains a differential value of the sampling value by averaging a previous sampling value and a next sampling value of the sampling value, and the differential value is used as the output of the first-order differential module. The error correction module is input into the product of the sampling value stored in the data buffer module, the output value of the first-order differential module and the adaptive iteration output value, and the error correction module obtains the output value of the error correction module by subtracting the product of the sampling value stored in the data buffer module, the output value of the first-order differential module and the adaptive iteration output value, wherein the output value is a correction result. And the input of the 1:4 data distributor module is an output value of the error correction module, and the data distributor module divides the input value into four paths of output values. The two-stage difference value operation module inputs four paths of output values of the 1:4 data distributor module, the two-stage difference value operation module subtracts two paths of adjacent values, takes absolute values of the subtracted values, averages the subtracted values to obtain four paths of expected values, and subtracts the obtained adjacent expected values to obtain three output values of the two-stage difference value o