CN-121984501-A - Low-cost rapid test system of ultra-high precision analog-to-digital converter

CN121984501ACN 121984501 ACN121984501 ACN 121984501ACN-121984501-A

Abstract

The invention discloses a low-cost rapid test system of an ultra-high-precision analog-to-digital converter, which comprises an upper computer, a test evaluation board, a power module and a power module, wherein the upper computer is used for generating and outputting test instructions, the differential linear error and the integral linear error of the to-be-tested ADC are obtained through calculation according to analog-to-digital conversion results output by the to-be-tested ADC under different excitation voltages, the test evaluation board is used for applying different excitation voltages to the to-be-tested ADC according to the test instructions, and the power module is used for supplying power to the test evaluation board. The test system does not require an excitation source to have higher resolution than the ADC to be tested, and compared with a histogram method, the number of samples required by the histogram method is greatly reduced, so that the economic cost and the time cost can be reduced, and the test efficiency of the ultra-high precision ADC is improved.

Inventors

QIAN JIN
ZHANG TIELIANG
TAN BO
LI DONGKANG
ZHANG XINXING
WANG CHUANZHONG
GONG JIANXUE
LI SHAOJIE

Assignees

北京微电子技术研究所

Dates

Publication Date: 20260505
Application Date: 20251218

Claims (10)

1. A low cost, fast test system for ultra-high precision analog-to-digital converters, comprising: The upper computer is used for generating and outputting a test instruction, and calculating to obtain a differential linear error and an integral linear error of the ADC to be tested according to analog-to-digital conversion results output by the ADC to be tested under different excitation voltages, wherein the ADC to be tested is an ADC with N-bit precision; The test evaluation board is used for applying different excitation voltages to the ADC to be tested according to the test instruction, and uploading the analog-to-digital conversion result output by the ADC to be tested under the different excitation voltages to the upper computer; and the power supply module is used for supplying power to the test evaluation board.
2. The low cost rapid test system of ultra-high precision analog-to-digital converter of claim 1, wherein the test evaluation board comprises: the FPGA module is used for controlling the ramp voltage generator and the offset voltage generator to apply different excitation voltages to the ADC to be tested through the analog adder according to the test instruction Analog-to-digital conversion result of lower output Will be Uploading to an upper computer; A ramp voltage generator for generating a ramp voltage under the control of the FPGA module ; An offset voltage generator for generating an offset voltage under the control of the FPGA module ; Analog adder for ramp voltage And offset voltage After forward and reverse scaling, the exciting voltage is output To the ADC to be tested; and the reference source circuit is used for providing reference voltage for the ADC to be tested.
3. The system of claim 2, wherein the ramp voltage generator is an M-bit precision DAC and the offset voltage generator is an L-bit precision DAC, wherein M < N, L < N.
4. A low cost fast test system for ultra high precision analog to digital converter according to claim 3, wherein the range of the DAC with M bit precision is the same as the range of the ADC to be tested, and the range of the DAC with L bit precision is half the range of the ADC to be tested.
5. The system for rapidly testing ultra-high-precision analog-to-digital converter with low cost according to claim 2, wherein the upper computer is configured to calculate differential linearity error and integral linearity error of the ADC to be tested according to analog-to-digital conversion results output by the ADC to be tested under different excitation voltages, when the differential linearity error and the integral linearity error are obtained, the system comprises: based on polynomial fitting, build And (3) with Nonlinear relationship between: ···(1) Wherein, the Representing polynomial fits A minor term coefficient; According to And (3) with Nonlinear relation between the two to obtain transfer function coefficient for describing conversion characteristics of ADC to be tested : ···(2) Wherein, the The difference value of the numerical polynomials output by the ADC to be tested under different offset voltages is represented; Then there are: ···(3) Wherein, the Representing the full scale voltage of the ADC under test, Representing the full scale voltage of an ideal ADC of N-bit precision, Represents a scaling constant that is set to a predetermined value, Representing a transpose; based on transfer function coefficients Obtaining the transfer function of the actual fitting of the ADC to be tested ; Transfer function according to the obtained actual fitting of ADC to be measured Transfer function of ideal ADC combined with N-bit precision And calculating to obtain the differential linear error and the integral linear error of the ADC to be measured.
6. The system of claim 5, wherein the transfer function of the actual fit of the ADC under test Transfer function of ideal ADC with N-bit precision Respectively expressed as follows ···(4) ···(5) Wherein, the Representing the input voltage.
7. The system of claim 6, wherein the transfer function is based on a resulting actual fit of the ADC under test Transfer function of ideal ADC combined with N-bit precision The differential linear error and the integral linear error of the ADC to be measured are obtained through calculation, and the method comprises the following steps: for each digital code, according to the transfer function of the actual fitting of the ADC to be tested Obtaining the maximum input voltage under the same digital code output And minimum input voltage According to And Calculating to obtain the voltage of the kth conversion midpoint of the ADC to be tested : ···(6) Transfer function of ideal ADC according to N-bit precision Calculating the voltage of the kth conversion midpoint of the ideal ADC with N-bit precision : ···(7) Wherein, the A voltage difference between two adjacent digital codes of an ideal ADC representing N-bit precision; According to And The differential linear error of the kth conversion code is obtained by the solution : ···(8) According to Solving to obtain integral linear error of the kth conversion code : ···(9)。
8. The low cost flash test system of an ultra-high precision analog-to-digital converter of claim 7, 。
9. The low cost, fast speed test system for ultra-high precision analog to digital converters of claim 2, The upper computer is also used for generating and outputting a working mode control instruction; The FPGA module is also used for generating SPI control codes for configuring the working modes of the slope voltage generator, the offset voltage generator and the ADC to be tested according to the working mode control instruction.
10. The low cost rapid test system of ultra-high precision analog-to-digital converter of claim 1, wherein the power module comprises: A power supply for providing a stable voltage output; the low-dropout linear voltage regulator is used for converting the voltage output by the power supply into the working voltage required by each module in the test evaluation board and supplying power for each module in the test evaluation board.

Description

Low-cost rapid test system of ultra-high precision analog-to-digital converter Technical Field The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a low-cost rapid test system of an ultra-high-precision analog-to-digital converter. Background As ADC resolution increases, the histogram approach becomes infeasible. Typically, the average number of samples per digital code is collected in a histogram method, ranging from 30 to 40 samples. To ensure test quality, one hundred or hundreds of samples may be required per code. A 24-bit resolution ADC consists of over 1600 tens of thousands of digital output codes (16,777,216 codes). When a 24-bit resolution ADC is tested by collecting an average of 100 samples per code using the histogram method, more than 16 hundred million samples need to be measured, and thus the data storage cost is very huge. Furthermore, the sampling rate of high-precision ADCs is typically much lower than high-speed low-precision ADCs, so collecting such a large number of samples at a low sampling rate means that the test time is long. Therefore, the histogram test is not suitable for high-precision ADC linearity test due to the long test time. And the histogram method requires that the resolution of the excitation source is greater than 3 to 4 bits of the ADC to be tested, so that the quality and price of the required audio source are higher and higher. Therefore, the conventional histogram method is not affordable in both time cost and economic cost. Disclosure of Invention The invention solves the technical problems of overcoming the defects of the prior art, providing a low-cost rapid test system of an ultra-high-precision analog-to-digital converter, aiming at solving the problems of overhigh time cost and equipment cost required by the conventional histogram method for testing the ultra-high-precision ADC static parameters, and effectively saving the test cost and the test time. In order to solve the technical problems, the invention discloses a low-cost rapid test system of an ultra-high precision analog-to-digital converter, comprising: The upper computer is used for generating and outputting a test instruction, and calculating to obtain a differential linear error and an integral linear error of the ADC to be tested according to analog-to-digital conversion results output by the ADC to be tested under different excitation voltages, wherein the ADC to be tested is an ADC with N-bit precision; The test evaluation board is used for applying different excitation voltages to the ADC to be tested according to the test instruction, and uploading the analog-to-digital conversion result output by the ADC to be tested under the different excitation voltages to the upper computer; and the power supply module is used for supplying power to the test evaluation board. In the low-cost rapid test system of the ultra-high precision analog-to-digital converter, the test evaluation board comprises: the FPGA module is used for controlling the ramp voltage generator and the offset voltage generator to apply different excitation voltages to the ADC to be tested through the analog adder according to the test instruction Analog-to-digital conversion result of lower outputWill beUploading to an upper computer; A ramp voltage generator for generating a ramp voltage under the control of the FPGA module ; An offset voltage generator for generating an offset voltage under the control of the FPGA module; Analog adder for ramp voltageAnd offset voltageAfter forward and reverse scaling, the exciting voltage is outputTo the ADC to be tested; and the reference source circuit is used for providing reference voltage for the ADC to be tested. In the low-cost rapid test system of the ultra-high-precision analog-to-digital converter, the slope voltage generator adopts a DAC with M-bit precision, and the offset voltage generator adopts a DAC with L-bit precision, wherein M is less than N, and L is less than N. In the low-cost rapid test system of the ultra-high-precision analog-to-digital converter, the measuring range of the DAC with M-bit precision is the same as the measuring range of the ADC to be tested, and the measuring range of the DAC with L-bit precision is half of the measuring range of the ADC to be tested. In the low-cost rapid test system of the ultra-high precision analog-to-digital converter, when the upper computer calculates to obtain the differential linear error and the integral linear error of the ADC to be tested according to the analog-to-digital conversion results output by the ADC to be tested under different excitation voltages, the system comprises: based on polynomial fitting, build And (3) withNonlinear relationship between: ···(1) Wherein, the Representing polynomial fitsA minor term coefficient; According to And (3) withNonlinear relation between the two to obtain transfer function coefficient for describing conversion characteristics of