CN-121984503-A - Self-calibration circuit for offset front end of high-speed comparator

CN121984503ACN 121984503 ACN121984503 ACN 121984503ACN-121984503-A

Abstract

The invention provides a self-calibration circuit of a high-speed comparator offset front end, and belongs to the technical field of analog-to-digital converter circuits in integrated circuit designs. The self-calibration circuit comprises a calibration logic circuit, a calibration voltage generation circuit, a comparator differential input pair tube back gate bias and a comparator, wherein the comparator and the comparator differential input pair tube back gate bias are components of an ADC circuit, and the calibration voltage generation circuit comprises a p-end calibration voltage generation circuit and an n-end calibration voltage generation circuit, and the two ends of the calibration voltage generation circuit are symmetrical in structure. According to the invention, the self-calibration logic is realized by multiplexing the original circuit of the ADC, only a small amount of calibration control logic and a counter are introduced, and the simple calibration voltage generating circuit is combined, so that the calibration voltage is fed back to the back grid of the differential input pair tube of the comparator, the offset voltage of the comparator is regulated in an approximation way by utilizing the body effect, and the low cost and high calibration precision are realized on the premise of not affecting the speed of the comparator.

Inventors

GUO XIAOFENG
CHEN RUN
CHEN ZHENQI
CHEN YONGGANG

Assignees

北京纽瑞芯科技有限公司

Dates

Publication Date: 20260505
Application Date: 20260112

Claims (5)

1. The high-speed comparator offset front end self-calibration circuit is characterized by comprising a calibration logic circuit, a calibration voltage generation circuit, a comparator differential input pair tube back gate bias and a comparator, wherein the comparator and the comparator differential input pair tube back gate bias are components of an ADC circuit, the calibration logic circuit, the calibration voltage generation circuit and the comparator are connected with each other, the calibration voltage generation circuit is also connected with the comparator differential input pair tube back gate bias input end, the comparator differential input pair tube back gate bias output end is connected with the comparator, and the calibration voltage generation circuit comprises a p-end calibration voltage generation circuit and an n-end calibration voltage generation circuit which are symmetrical in structure.
2. The self-calibration circuit of claim 1, further comprising: the calibration logic circuit is also provided with a sampling module and a conversion logic module of a multiplexing ADC circuit, and is used for generating a differential 0 signal and outputting the differential 0 signal to a differential input end of the comparator; The comparator is used for outputting a differential pulse signal related to the offset voltage sign to the calibration voltage generation circuit, wherein the differential pulse signal comprises a pulse p and a pulse n; The calibration voltage generation circuit is used for generating calibration voltage according to the received differential pulse signal and outputting the calibration voltage to the back gate bias of the input differential pair tube of the comparator, wherein the pulse p is used as a driving clock of the p-end calibration voltage generation circuit, the pulse n is used as a driving clock of the n-end calibration voltage generation circuit, if the offset is positive, the pulse p drives the p-end calibration voltage generation circuit to perform primary calibration voltage FBp approximation, and if the offset is negative, the pulse n drives the n-end calibration voltage generation circuit to perform primary calibration voltage FBn approximation; And the comparator inputs back gate bias of the differential pair tube and is used for calibrating the offset of the comparator according to the received calibration voltage so that the offset voltage approaches zero.
3. The self-calibration circuit of claim 2, further comprising: the p-end calibration voltage generation circuit and the N-end calibration voltage generation circuit comprise N D triggers with set, N+1 resistors and N NMOS tubes.
4. The self-calibration circuit of claim 3, further comprising: In the p-terminal calibration voltage generation circuit, clk terminal of each D trigger is connected with pulse p, set terminal is connected with reset signal, D terminal of first-stage D trigger is 0, Q terminal of first-stage D trigger is connected with D terminal of second-stage D trigger, from second-stage D trigger to start, Q terminal of each stage D trigger is connected with D terminal of next-stage D trigger, and cascade connection is conducted in turn until N-th stage D trigger is reached, power supply VDD is connected in series with ground through resistors R0 and R1 to RN in turn, wherein one end of R0 is connected with VDD, the other end is connected with calibration voltage output FBp, RN is grounded, drain electrodes of N NMOS tubes are respectively connected with N resistor series connection nodes, grid electrodes are respectively connected with Q terminal output of N D triggers, Q1 of first-stage D trigger is connected with first NMOS grid electrode, Q2 of second-stage output Q2 is connected with second NMOS grid electrode, and QN-th output QN is connected with N-th NMOS grid electrode.
5. A self-calibration method based on the self-calibration circuit of claim 3, comprising: 1) The calibration is started, a calibration logic circuit is enabled, a counter module in the calibration logic circuit starts counting, and the calibration logic controls and multiplexes the ADC circuit; 2) The calibration logic circuit controls a sampling module of a lower polar plate in the ADC circuit to be closed, and an upper polar plate normally samples a common mode signal to generate a differential 0 signal and outputs the differential 0 signal to the comparator; 3) The calibration logic circuit controls a conversion logic module in the ADC circuit to be closed, and keeps the differential input of the comparator to be 0; 4) The comparator outputs a differential pulse signal to drive the calibration voltage generating circuit to generate calibration voltage, wherein a pulse p is used as a driving clock of the p-end calibration voltage generating circuit, and a pulse n is used as a driving clock of the n-end calibration voltage generating circuit; 5) The calibration voltage acts on the back gate bias of the input differential pair transistor of the comparator, so that the offset voltage approaches zero once, and the approximation step length is approximately equal to the total offset calibration range divided by N; 6) And judging that if the count value of the counter module is smaller than N, returning to the step 2) again to continue calibration, and if the count value reaches N, closing the calibration logic circuit, and enabling the ADC circuit to enter a normal working mode.

Description

Self-calibration circuit for offset front end of high-speed comparator Technical Field The invention belongs to the technical field of analog-to-digital converter (ADC) circuits in integrated circuit design, and particularly relates to a self-calibration circuit at the offset front end of a high-speed comparator. Background The high speed comparator is the core module of the high speed ADC, its speed determines the conversion speed of the ADC. Comparator misalignment is a non-ideal factor inherent to comparators, and in modern mainstream CMOS processes is mainly caused by process mismatch (including threshold voltage Vth mismatch and current Id mismatch of transistors) and layout mismatch. Layout mismatch can be eliminated by good symmetry design, while process mismatch is only related to device size and process mismatch parameters of the comparator. At the design level, process mismatch can be reduced by increasing device size resulting in comparator mismatch (typically mismatch is inversely proportional to square root of the size), but larger device size introduces more parasitic capacitance, thereby increasing kick-back noise and reducing comparator speed. Thus, in applications requiring low offset voltages, it is often desirable to introduce offset calibration to further suppress comparator offset. Currently, comparator offset calibration in ADCs is largely divided into analog front-end calibration and digital back-end calibration. Analog front end calibration mainly includes the following ways: self-zeroing/bootstrapping and chopping-self zeroing techniques introduce kT/C noise and bandwidth loss by sampling and counteracting static misalignment, but require two or more phases and introduce switching and sampling capacitance. In multi-GS/s applications, sampling phase occupation can reduce the effective data throughput rate. The chopping technique can shift the low frequency offset, but the chopping frequency conflicts with the regeneration process, and the modulation residual introduced by the switch is significant at high frequencies and thus not suitable for high speed comparators. And the capacitor/current injection type offset is realized by adopting CDAC or IDAC to inject equivalent bias into an input pair or a regeneration node, and the method is suitable for one-time or online calibration. The precision is limited by the minimum bit (LSB) of the DAC, the mismatch of the cells and the reference drift, and the capacitance is increased or the current is reduced to obtain smaller LSB, the input load is increased and the kickback noise is generated, and the noise and the leakage current are limited, so that the speed is not improved. Injecting calibration into the regeneration node reduces the impact on input bandwidth, but changes the regeneration pole and positive feedback coefficient, with the cost of speed and power consumption. The body effect/tail current tuning is realized by programmable threshold bias, body end bias or tail current adjustment, the comparator speed is not affected generally, and the method is suitable for high-speed scenes. But additional complex circuitry is required to implement the measurement and calibration control words for comparator offset. The preamplifier counteracts that the low offset amplifier is added in front of the latch and self-zeroing is carried out, so that equivalent offset can be reduced and regeneration can be accelerated. However, the pre-amplifier itself consumes power, increases delay and noise, and also occupies timing resources from zero, which is not suitable for high-speed comparators. Digital back-end calibration is the main solution to eliminate ADC offset, including comparator offset, and its core is to directly measure and subtract offset in the digital domain. The method based on redundant bit, histogram or correlation estimation is suitable for background calibration of architecture such as SAR, pipeline and the like by estimating and compensating offset of the comparator in a digital domain. The method has the advantages of small front-end load, small influence on speed, strong self-adaption to process, voltage and temperature (PVT) change, and the defects of needing statistic time and additional logic, being influenced by input distribution and algorithm, being incapable of directly correcting the instantaneous threshold of single decision and being difficult to restrain dynamic mismatch and metastable state behavior during high-speed regeneration. The accuracy is limited by quantization, noise and data correlation, and in time interleaved ADC, independent estimation per channel is required, and the system complexity is high. A one-time factory digital fuse (eFuse) or register trim (trim) can reduce manufacturing offset, but increase testing time and cost, and are difficult to cover temperature, power supply, and aging and drift, and have insufficient field accuracy and reliability. In addition, another limitation of digital offset calib