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CN-121984504-A - ADC time domain error background calibration method and system based on digital output statistics

CN121984504ACN 121984504 ACN121984504 ACN 121984504ACN-121984504-A

Abstract

The invention discloses an ADC time domain error background calibration method and system based on digital output statistics, which comprises a digital signal monitoring module, a gain error calibration module and a hierarchical level offset error calibration module, wherein digital signals output by a front end and a rear end of an ADC are obtained through connecting the front end and the rear end of the ADC and carrying out real-time monitoring on the digital signals, the offset error direction of a voltage-time converter VTC is extracted and regulated by utilizing the different same relation between the saturation state of the rear end ADC and the MSB of the front end and the rear end, a hierarchical level offset calibration loop is constructed and decoupling calibration is carried out on each path offset of VTC and TDC, and the simultaneous, real-time and high-robustness calibration on gain errors and multisource offset errors is realized on the premise of no interruption and low cost, and the method belongs to the technical field of mixed signal integrated circuits.

Inventors

  • TANG XIYUAN
  • WANG JINGPENG

Assignees

  • 北京大学

Dates

Publication Date
20260505
Application Date
20260120

Claims (8)

  1. 1. The ADC time domain error background calibration method based on digital output statistics is characterized by comprising the following steps of: step one, monitoring and acquiring digital signals output by a front-end stage and a rear-end stage in real time; The digital signal at least comprises MSB which is the most significant bit output by the front-end time-digital converter TDC, MSB TDC , MSB backend which is the most significant bit output by the back-end analog-digital converter ADC, a back-end ADC saturation flag signal which is generated by the back-end ADC and indicates that the input is over-range, and a TDC saturation flag signal which is generated by the front-end TDC and indicates that the quantization is over-range; Step two, gain error judgment and calibration are carried out, namely the direction of the VTC gain error of the voltage-time converter is extracted and regulated by utilizing the different and same relation between the saturated state of the back-end ADC and the MSB of the front end and the back end; Step three, calibrating a hierarchical offset error; Establishing a hierarchical offset calibration loop based on path selection characteristics of a differential folding architecture, wherein a main offset calibration loop indirectly counteracts VTC offset by calibrating positive/negative paths respectively, and an auxiliary offset calibration loop directly intervenes in VTC calibration under the saturated extreme condition; the method for decoupling and calibrating the inherent offset of the VTC and the offset of each path of the TDC by adopting the constructed main offset calibration loop and auxiliary offset calibration loop comprises the following steps: 31 Main detuned loop calibration mode): Using MSB TDC as a path select signal, the total offset error is attributed to either the positive or negative side TDC path; selecting a positive end calibration path, counting the error direction of total offset by using the symbols of MSB backend , and adjusting the delay amount of the positive end TDC so as to enable the total offset to converge; Selecting a calibration path of a negative terminal, counting the error direction of total offset by using the sign of MSB backend , and adjusting the delay amount of the TDC of the negative terminal to enable the total offset to be converged; 32 Auxiliary detuning loop calibration employs saturation recovery mode: Monitoring a TDC saturation mark signal in real time; Judging whether saturation is carried out according to the TDC saturation mark signal, if saturation is carried out, freezing the main detuning loop, and activating the auxiliary detuning loop; After the main detuning loop is frozen and the auxiliary detuning loop is activated, the detuning adjusting unit in the VTC is directly adjusted by utilizing the symbol statistical error direction of the MSB backend until the TDC saturation flag signal is unsaturated, and the main detuning loop is returned to the main detuning loop calibration mode.
  2. 2. The method of calibrating ADC time domain error background based on digital output statistics as set forth in claim 1, wherein step two of performing gain error determination and calibration specifically designs logic determination rules for determining that VTC gain is too small or VTC gain is too large by utilizing different relationships between saturation states of a back-end ADC and front-end MSBs, extracts a VTC gain error direction of a voltage-to-time converter, and executes a corresponding gain adjustment instruction.
  3. 3. The method for calibrating ADC time-domain error background based on digital output statistics according to claim 2, wherein the logic judgment rule is specifically: when the rear-end ADC saturation flag signal is monitored to be logic 1, namely the rear-end ADC is saturated, and the MSB TDC and the MSB backend are equal in logic value, namely in phase, the VTC gain is judged to be too small; when the back-end ADC saturation flag signal is monitored to be logic 1, i.e., the back-end ADC is saturated, and the MSB TDC and MSB backend are not equal in logic value, i.e., inverted, it is determined that the VTC gain is excessive.
  4. 4. The ADC time-domain error background calibration method according to claim 2, wherein the performing of the corresponding gain adjustment command according to the VTC gain error direction comprises: Configuring a gain oversize statistical counter and a gain undersize statistical counter, respectively corresponding to the events of the excessive gain of the VTC and the undersize gain of the VTC, and setting a preset gain counting threshold; accumulating the corresponding counters according to the judgment result; When the excessive gain statistics counter value reaches a threshold value, the output gain adjustment instruction is that the VTC gain is reduced, and the counter is reset; When the value of the statistic counter with the excessively small gain reaches a threshold value, the output gain adjusting instruction is that the gain of the VTC is increased, and the counter is reset; in response to the output gain adjustment command, the conversion gain of the VTC is corrected by adjusting the bias current or slope control voltage of the VTC.
  5. 5. The ADC time-domain error background calibration method according to claim 1, wherein step 31) the main offset loop calibration mode is specifically: When MSB TDC =1, the folding TDC selects the positive end TDC for quantization, and the offset T os,TDC,p of the positive end TDC path is superimposed on the total offset, which is equal to T os,eq = T os,vtc + T os,TDC,p ; Selecting a positive end calibration path, counting the error direction of total offset by using the symbols of MSB backend , and adjusting the delay amount of the positive end TDC to enable the total offset T os,eq to be converged to 0; When MSB TDC = 0, folding TDC selects negative side TDC for quantization, where the offset T os,TDC,n of the negative side TDC path is superimposed on the total offset, which is equal to T os,eq = -T os,vtc + T os,TDC,n ; The negative side calibration path is selected, the error direction of the total offset is counted by using the sign of the MSB backend , and the delay amount of the negative side TDC is adjusted, so that the total offset T os,eq is converged to 0.
  6. 6. The ADC time domain error background calibration system based on digital output statistics realized by the method of any one of claims 1-5, which is characterized by comprising a digital signal monitoring module, a gain error calibration module and a hierarchical offset error calibration module, wherein: The digital signal monitoring module is used for acquiring the MSB TDC 、MSB backend , the saturation mark signal of the ADC at the rear end and the TDC saturation mark signal of the TDC at the front end in real time by connecting the front end and the rear end of the ADC; The gain error calibration module is used for judging and calibrating gain errors, and extracting and adjusting the gain error direction of the voltage-time converter VTC by utilizing the different and same relation between the saturated state of the back-end ADC and the MSB of the front end and the back end; The hierarchical offset error calibration module is used for constructing a main offset calibration loop and an auxiliary offset calibration loop, and performing decoupling calibration on the inherent offset of the VTC and the offset of each path of the TDC through the hierarchical offset calibration loop.
  7. 7. The ADC time-domain error background calibration system according to claim 6, wherein the gain error calibration module comprises a logic decision unit, a gain statistics unit, and a gain adjustment unit, wherein: The logic decision unit is used for configuring an exclusive nor (exclusive nor) and an exclusive nor (exclusive nor) logic circuit, comparing MSB TDC with MSB backend and outputting a pulse signal with overlarge gain or overlarge gain by combining a rear-end ADC saturation mark signal; The gain statistics unit comprises a gain oversized statistics counter and a gain undersized statistics counter, counts the pulse signals with oversized gain or undersized gain respectively, generates an adjustment trigger signal when the count value reaches a preset threshold value, and resets the count value; The gain adjusting unit comprises a gain adjusting charge pump and a bias adjusting circuit connected with the VTC, and responds to the trigger signal to adjust the charging current or capacitance of the VTC so as to change the gain of the VTC.
  8. 8. The ADC time-domain error background calibration system according to claim 6, wherein the hierarchical misalignment error calibration module comprises a primary misalignment calibration loop and a secondary misalignment calibration loop, wherein: The main offset calibration loop comprises a positive offset statistics counter, a negative offset statistics counter and a delay adjustment charge pump which are respectively connected to a positive end TDC and a negative end TDC, wherein the main calibration loop activates the positive end counter or the negative end counter according to the high and low level of an MSB TDC , counts the MSB backend and feeds back to adjust the internal delay of the TDC; The auxiliary offset calibration loop comprises a VTC offset statistics counter and a VTC offset adjustment charge pump, and is enabled to directly adjust the mismatch of the input pair of the voltage-time converter by using the statistics result of the MSB backend when the auxiliary calibration loop detects that the TDC saturation flag signal is logic 1.

Description

ADC time domain error background calibration method and system based on digital output statistics Technical Field The invention belongs to the technical field of mixed signal integrated circuits, relates to a high-speed and high-precision analog-digital converter (ADC), and particularly relates to an ADC time domain error background calibration method and system based on digital output statistics, wherein only digital domain information is used for carrying out real-time background calibration on the ADC front end time domain error of a time domain architecture. Background With the rapid development of modern communication, radar, precision instruments and other technologies, unprecedented demands are placed on the core performance index of an analog-to-digital converter (ADC) capable of converting analog signals to digital signals at high speed and with high fidelity. Among many ADC architectures, pipelined ADCs are important due to their excellent balance in speed and accuracy. In particular, to further break through the speed bottleneck and optimize power consumption, pipelined ADCs that incorporate time-domain quantization techniques, i.e., architectures in which the front-end stages employ voltage-to-time converters (VTCs) and time-to-digital converters (TDCs), have become hot spots for leading-edge research and application. However, the overall performance of such a time domain architecture ADC is highly dependent on the stability of its analog front end, especially the VTC. Two key performance parameters of VTC, namely gain (defining the proportional relationship of input Voltage variation to output time variation) and offset (defining the inherent time offset generated when zero input Voltage), exhibit high sensitivity to variations in Process corner (Process), voltage supply when the chip is operating, and ambient Temperature (collectively PVT) during semiconductor manufacturing. Real-time drift of the VTC gain and offset parameters caused by these PVT factors can directly introduce conversion errors, significantly reducing the effective resolution, signal-to-noise ratio, and dynamic range (SNDR) of the ADC, and even leading to functional failure. To address this challenge, the prior art developed a variety of calibration schemes, but each had its limitations: 1. Foreground calibration Foreground Calibration such methods measure and correct errors in the VTC during the system power-up initialization phase or by periodically interrupting the normal data conversion tasks of the ADC, inputting one or more accurate reference voltages. The fundamental drawback of this approach is its "off-line" nature, which does not track and compensate for real-time parameter drift due to voltage fluctuations or temperature variations during continuous operation of the ADC. 2. Background calibration based on analog copies (Replica-Based Background Calibration) this approach integrates an analog copy VTC with a structure that matches as much as possible beside the VTC of the main signal path. The replica circuit is continuously calibrated by an analog feedback loop and its calibration result (e.g., a control voltage) is applied to the master VTC. The main problem with this approach is that the process mismatch that must exist between the master and replica circuits can limit the final accuracy of the calibration. In addition, the complex analog replica and feedback loop introduce significant additional chip area, power consumption, and design complexity. 3. Redundancy-based background calibration (Redundancy-Based Background Calibration) this method provides room for offset errors to be detected and corrected by adding extra quantization bits (Redundancy) in the TDC. However, such techniques are generally only effective for offset errors, and have limited or no ability to calibrate for the same critical gain errors. In summary, a new background calibration technology is urgently needed at present, which can be performed on the premise of not interrupting the normal operation of the ADC, and no additional complex analog circuit is required to be introduced, so as to reduce cost and design risk, and simultaneously and accurately calibrate two key time domain errors of gain and offset. Disclosure of Invention In order to solve the problems of large hardware cost, incapability of tracking PVT changes in real time, incomplete calibration or strong architecture dependence in the prior time domain architecture ADC error calibration technology, the invention provides an ADC time domain error background calibration method and system based on digital output statistics. The invention designs a background calibration framework without analog copy based on digital domain statistics, which is characterized in that a logic relation of a front end ADC saturation zone bit and a front end and a rear end most significant bit (Most Significant Bit, MSB for short) is utilized to extract a gain error direction of a Voltage-to-Time Converter