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CN-121984506-A - Capacitance mismatch calibration method and circuit of high-precision successive approximation type analog-to-digital converter

CN121984506ACN 121984506 ACN121984506 ACN 121984506ACN-121984506-A

Abstract

The invention discloses a capacitance mismatch calibration method and circuit of a high-precision successive approximation type analog-digital converter, and relates to the technical field of analog-digital converters, wherein after the analog-digital converter finishes conversion once, a turnover and comparison mechanism is triggered by detecting a specific digital code to realize on-line detection of high-order Duan Dianrong mismatch, when inconsistent comparison results are detected, a calibration flow is automatically started, an initial compensation digital code is generated by taking the lowest-order capacitance in a high-order capacitance array as the starting point based on comparison errors, unit capacitance in an LSB repeated capacitance is introduced to participate in iterative calibration, a high-precision compensation result is obtained by independently calibrating for many times and taking an average value, and finally, the self-adaptive correction of the capacitance mismatch errors is realized by using the compensation digital code, and the bitwise calibration of the high-order capacitance is finished according to the sequence from low to high; the invention detects the mismatch error of the capacitor with high weight on line and compensates in a self-adaptive way, thereby obviously improving the conversion precision and the dynamic performance of the analog-digital converter.

Inventors

  • DENG HONGHUI
  • CHEN MING
  • SONG XINGGUO
  • LU ZHONGXING
  • WU YINGMIN
  • YIN YONGSHENG

Assignees

  • 合肥工业大学

Dates

Publication Date
20260505
Application Date
20260126

Claims (10)

  1. 1. The method is characterized in that the analog-to-digital converter comprises a capacitor array module, a comparator module and a control module, wherein the capacitor array module comprises a P-end capacitor array and an N-end capacitor array, a preset number of LSB repeated capacitors are respectively arranged in high-order section capacitor arrays corresponding to the P-end capacitor array and the N-end capacitor array, the method is used for calibrating after the analog-to-digital converter completes single conversion and obtains an output digital code, and the calibration process specifically comprises the following steps: step 1, differential comparison is carried out on voltages of a P end and an N end of a capacitor array module by using a comparator module, and a binary number code D A is obtained based on a comparison result; Step 2, verifying whether the digital code D A is consistent with a preset calibration digital code, if not, not starting the calibration, if so, generating a clock signal, turning the digital code D A to the digital code D B based on the clock signal, adjusting the switch connection state of the capacitor array module by using the control module according to D B , acquiring a new digital code D ' A by using the comparator module, if D ' A is consistent with the original digital code D A , not starting the calibration, if D ' A is inconsistent with the original digital code D A , starting the calibration, and executing step 3; And 3, calibrating the lowest-order capacitor in the high-order section capacitor array to obtain a corresponding compensation digital code, wherein the method specifically comprises the following steps of: Step 31, using the lowest capacitance in the high-order capacitor array as a target capacitance, and generating an initial compensation digital code delta Di based on an error between a digital code by corresponding to the target capacitance in the original digital code D A and a digital code by 'corresponding to the target capacitance in the new digital code D' A in a time period corresponding to the current clock; step 32, for single-group LSB repeated capacitors, selecting a unit capacitor from the single-group LSB repeated capacitors to participate in calibration, superposing an initial compensation digital code DeltaDi on a digital code D B , adjusting the switch connection state of a capacitor array module by using a control module based on the superposition result, performing differential comparison on voltages of a P end and an N end corresponding to a target capacitor by using a comparator module to obtain an updated single-group digital code bx, if bx is the same as by, ending the iteration, if bx is different from by, updating the compensation digital code DeltaDi based on the error of bx and by, superposing the updated compensation digital code DeltaDi on a digital code D B , acquiring the single-group digital code bx again, iterating until bx is the same as by, ending the iteration, and storing the compensation digital code DeltaDi corresponding to the last iteration as an intermediate compensation digital code corresponding to the current target capacitor; Step 33, traversing each unit capacitor in the LSB repetition capacitor in a mode of step 32, obtaining a plurality of intermediate compensation digital codes, and taking the average value of all the intermediate compensation digital codes as a final compensation digital code corresponding to the current target capacitor; step 4, multiplying the original digital codes corresponding to each group of high-order capacitors in the output digital codes with the final compensation digital codes, accumulating the products of each group, and superposing the accumulated value on the original output digital codes to obtain calibrated output digital codes; and 5, generating a new clock signal after the calibration is finished, repeatedly executing the steps 1 to 2 after the next analog-to-digital conversion, calibrating the secondary low-order capacitance in the high-order section capacitance array after the next starting calibration, traversing each position of capacitance to be calibrated in the high-order section capacitance array in a mode from low to high, and acquiring the calibrated output digital code after each analog-to-digital conversion by the method of the step 4 after traversing.
  2. 2. The method for calibrating the capacitance mismatch of the high-precision successive approximation analog-to-digital converter as set forth in claim 1, wherein the step 1 specifically includes: The differential input signals V IN and V IP are kept at the N end and the P end of the capacitor array module by utilizing the sample hold module, the P end voltage and the N end voltage of each capacitor are subjected to differential comparison by utilizing the comparator module in sequence, when the P end voltage is higher than the N end voltage, a high level 1 is output, when the P end voltage is lower than the N end voltage, a low level 0 is output, and finally, a 17-bit binary number code DA is obtained.
  3. 3. The method for calibrating the capacitor mismatch of the high-precision successive approximation analog-to-digital converter as set forth in claim 1, wherein the step 2 specifically includes: For each capacitor in the high-order segment capacitor array, a corresponding predetermined calibration digital code D s ,D s = b16b15b 14..b 10b9 r..b 3b2b1, the predetermined calibration digital code corresponding to the lowest order capacitance in the high order segment capacitance array is xxx.100. The predetermined calibration digital codes corresponding to the secondary low-order capacitors in the high-order capacitor array are xxx, 1000, xxx and xxx 0111, xxx, and the predetermined calibration digital codes D s corresponding to each-order capacitor in the high-order capacitor array are obtained by analogy; verifying whether the digital code D A is consistent with D s corresponding to the current capacitance to be calibrated, if not, not starting calibration, if so, detecting that the logic output is 1, selecting a clock signal ck_10 corresponding to the lowest capacitance in the high-order section capacitance array, turning over the digital code D A to the digital code D B based on the clock ck_10, wherein only the specific digital code corresponding to the preset calibration digital code corresponding to the current coincidence in the digital code D A is turned over, if the digital code D A is xxx..100..xxx, turning over the specific digital code to be xxx..011..xxx, if the digital code D A is xxx..011..xxx, turning over the specific digital code to be xxx..100..xxx, and the like, so as to obtain the turned-over digital code D B .
  4. 4. The method for calibrating capacitor mismatch of high-precision successive approximation analog-to-digital converter as set forth in claim 3, wherein said step 2 further comprises: The differential input signals V IN and V IP are kept in a high-order Duan Dianrong array by utilizing a sample-hold module, then the lower plates of the P end and the N end capacitors in the high-order section capacitor array are respectively connected to the V CM end by utilizing a control module, then the connection method of each lower plate of the capacitors in the capacitor array module is controlled according to a digital code D B , when the digital code in D B is 0, the lower plate of the P end capacitor is connected with the GND end, the lower plate of the N end capacitor is connected with the V REF end, when the digital code in D B is 1, the lower plate of the P end capacitor is connected with the V REF end, the lower plate of the N end capacitor is connected with the GND end, and the differential comparison is carried out by utilizing a comparator module again to obtain a new digital code D' A ; And comparing a first target digital code corresponding to the preset calibration digital code which is currently consistent with the new digital code D' A with a second target digital code corresponding to the original digital code D A , judging that the high-order section capacitor array has no mismatch if the first target digital code is consistent with the second target digital code, not starting calibration, judging that the high-order Duan Dianrong array has mismatch if the first target digital code is inconsistent with the second target digital code, and starting calibration.
  5. 5. The method for calibrating the capacitor mismatch of the high-precision successive approximation analog-to-digital converter as set forth in claim 1, wherein the step 31 specifically includes: The digital codes by and the digital codes by 'are input into an exclusive-or gate logic module, at the moment, by and by' are different, the output error of the exclusive-or gate logic module is 1, an initial compensation digital code DeltaDi (1) corresponding to the current target capacitance is generated based on the error, and an iteration formula corresponding to the compensation digital code DeltaDi (k) is as follows: ; ; Where Δdi (k) is the compensated digital code generated in the kth iteration, the initial compensated digital code Δdi (1) = , Is a single digit code, a symbol The direction of compensation for compensating the digital code.
  6. 6. The method for calibrating the capacitor mismatch of the high-precision successive approximation analog-to-digital converter as set forth in claim 5, wherein said step 32 specifically comprises: The method comprises the steps of superposing the currently acquired compensation digital codes DeltaDi (k) on a digital code D B to obtain D B +△Di (k) , respectively connecting lower plates of P-end and N-end capacitors in a high-level capacitor array to a V CM end by using a control module, controlling connection of lower plates of each capacitor in the capacitor array module according to the digital codes D B +△Di (k) , carrying out differential comparison on voltages of the P-end and the N-end corresponding to a target capacitor by using a comparator module to obtain a new single-group digital code bx, inputting the digital codes by and the digital codes bx into an exclusive OR gate logic module, outputting an error of 0 by the exclusive OR gate logic module if bx is the same as bx, ending iteration, outputting an error of 1 by the exclusive OR gate logic module if by is different from bx, generating a new compensation digital code DeltaDi (k+1) based on the error, superposing (k+1) on the digital codes D B , and obtaining the single-group digital code bx again until the iteration is the same as bx.
  7. 7. The method for calibrating capacitor mismatch of high-precision successive approximation analog-to-digital converter as set forth in claim 6, wherein said step 33 specifically comprises: For any group of LSB repetition capacitors in the LSB repetition capacitors, selecting one unit capacitor from the rest unit capacitors, repeating the calibration step in the step 32, acquiring the intermediate compensation digital codes corresponding to the current target capacitor again, traversing each unit capacitor in the single group of LSB repetition capacitors in the mode, acquiring a plurality of intermediate compensation digital codes, calculating the average value of the plurality of intermediate compensation digital codes, taking the average value as the final compensation digital code corresponding to the current target capacitor, and expressing the average value of the plurality of intermediate compensation digital codes as: ; In the formula, For the nth intermediate compensated digital code, n=1, 2,..n, N is the number of unit capacitors in the single set of LSB repetition capacitors, And finally compensating the digital code for the current target capacitance.
  8. 8. The method for calibrating capacitor mismatch of high-precision successive approximation analog-to-digital converter as set forth in claim 7, wherein said step 4 specifically comprises: original digital codes Do_i corresponding to each group of capacitors in the output digital codes Do and final compensation digital codes Multiplying, accumulating the products of each group, and superposing the accumulated value on the original output digital code Do to obtain a calibrated output digital code Expressed as: ; In the formula, In order to output an original digital code corresponding to an ith high-order capacitor in the digital code Do, i=1, 2, M is the number of other capacitors to be calibrated except for the LSB repetition capacitor in the high-order capacitor array, and 17 bits of output digital codes are output The 16-bit output code D OUT is converted.
  9. 9. The capacitor mismatch calibration circuit of the high-precision successive approximation type analog-to-digital converter is characterized by comprising a sample and hold module, a capacitor array module, a control module, a comparator module and a digital calibration module; The capacitor array module comprises a P-end capacitor array and an N-end capacitor array, a preset number of LSB repeated capacitors are respectively arranged in high-order section capacitor arrays corresponding to the P-end capacitor array and the N-end capacitor array, each unit capacitor is used for being recycled in a calibration stage to obtain an average compensation digital code corresponding to a target capacitor which is calibrated currently, and the LSB repeated capacitors of the P-end and the N-end are symmetrically distributed; the sampling and holding module is respectively connected with the P-end capacitor array and the N-end capacitor array and is used for respectively transmitting and holding differential input signals V IN and V IP at the N end and the P end of the capacitor array module; the non-inverting input end and the inverting input end of the comparator module are respectively connected with the P end and the N end of the capacitor array module, and the output end of the comparator module is connected with the control module; the control module is connected with the digital calibration module and is used for adjusting the switch connection state of the capacitor array module according to the digital code fed back by the digital calibration module; The digital calibration module is used for turning over the specific digital code D A to the digital code D B after the specific digital code D A is detected, feeding back the D B to the control module, adjusting the switch connection state of the capacitor array module according to the D B by the control module, enabling the comparator module to update the digital code D A , comparing the original digital code D A with the updated digital code D A , judging whether to start calibration according to a comparison result, generating a compensation digital code based on error iteration between the updated digital code and the original digital code D A after the calibration is started, adjusting the switch connection state of the capacitor array module according to the D B and the compensation digital code by the control module, outputting a final compensation digital code after the iteration is finished, and calibrating the output digital code obtained by current analog-digital conversion based on the final compensation digital code.
  10. 10. The circuit of claim 9, wherein the digital calibration module comprises a specific digital code detection and flip module, a counter and register module, an exclusive-OR gate logic module, a first adder, a second adder, an LMS algorithm iteration module, an adder redundancy output module, a multiplier module, and an accumulation module; the specific digital code detection and turnover module is used for receiving the digital code D A output by the control module and turning over the digital code D B after detecting the specific digital code D A , feeding the digital code D B back to the first adder, and the counter and the register module are used for adding one after the calibration of the current capacitance is finished so as to drive the specific digital code detection and turnover module to switch to a calibration control clock corresponding to the next capacitance, thereby realizing the orderly calibration process of the high-level capacitance array from low level to high level; The input end of the exclusive-OR gate logic module is connected with the LMS algorithm iteration module, the input end of the LMS algorithm iteration module is respectively provided with a first adder, a counter and a register module, the exclusive-OR gate logic module is used for receiving the original digital code D A and the iteratively updated digital code D A , comparing and iterating the two to generate corresponding errors, the LMS algorithm iteration module is used for generating a compensating digital code DeltaDi according to the error iteration and feeding back the compensating digital code DeltaDi to the first adder, the first adder is used for superposing the digital code D B and the compensating digital code DeltaDi and feeding back the compensating digital code to the control module, and the counter and the register module are also used for storing the generated final compensating digital code after each calibration iteration is finished; The output end of the counter and register module is connected with the adder redundancy output module through the multiplier module, the accumulation module and the second adder in sequence, the counter and register module is also used for transmitting all final compensation digital codes to the multiplier module, the multiplier module is used for multiplying the original digital codes corresponding to each group of high-order capacitors in the output digital codes and the final compensation digital codes and transmitting the products to the accumulation module, the accumulation module is used for accumulating each group of products and superposing the accumulated value on the original output digital codes to obtain the calibrated output digital codes, and the adder redundancy output module is used for converting the output digital codes into output digital codes.

Description

Capacitance mismatch calibration method and circuit of high-precision successive approximation type analog-to-digital converter Technical Field The invention relates to the technical field of analog-to-digital converters, in particular to a capacitance mismatch calibration method and circuit of a high-precision successive approximation type analog-to-digital converter. Background With rapid development of technology, an analog-to-digital converter (ADC) capable of converting natural analog quantity into digital quantity is increasingly important. Among the many ADCs, successive approximation analog-to-digital converters (SAR ADCs) that have low power consumption, small size, and simple structure have received extensive research and attention. The high-precision and low-power-consumption SAR ADC is greatly demanded in the fields of sensors, medical electronics, portable equipment and the like at present, however, along with the improvement of SAR ADC digit, the signal amplitude required to be resolved by the ADC is smaller and smaller, and a plurality of non-ideal factors, especially the limitation of capacitance mismatch on the ADC precision, are more and more serious, so that great challenges are brought to the design of the high-precision SAR ADC. Thus, in high accuracy SAR ADC designs, capacitance mismatch is a problem that must be considered, and in general, the accuracy of SAR ADCs that do not use calibration is difficult to exceed 12 bits. In order to achieve good performance and high accuracy, calibration of capacitor mismatch is inevitably performed, and meanwhile, with the rapid development of digital circuit performance, the capacitor mismatch calibration method has the advantages of small area, low power consumption, high speed and the like, so that it becomes important to apply a digital calibration technology to improve the accuracy of the SAR ADC. The traditional capacitance mismatch calibration method comprises the following steps of accurately extracting mismatch information based on auxiliary DAC calibration, reducing calibration accuracy caused by capacitance mismatch of the auxiliary DAC due to the fact that calibration capability is limited by accuracy of the DAC, calibrating based on a statistical method, generally having delay and needing a large amount of data samples, influencing convergence speed, enabling the higher the accuracy is, the more sample data are needed, and the slower the speed is, so that the problems of calibration speed and timeliness are considered, the method is generally used for medium-accuracy calibration, error information is extracted through double conversion based on a disturbance calibration algorithm by utilizing a linear superposition principle, then an LMS algorithm updating weight is driven, the defects of the method are that power consumption is increased due to the fact that each sampling needs to be quantized twice, and simultaneously convergence speed is also slow due to the fact that the double-channel switching is needed, the calibration is difficult to drive weight update when the mismatch is consistent based on the split of a capacitor array, the calibration is slow due to the fact that a large amount of switch arrays are needed, the higher the calibration is not suitable for high-accuracy calibration, the error is not suitable for the high-accuracy calibration due to the fact that the high-accuracy SAR is needed, the error is not accumulated by the high-order calibration method is compared with the auxiliary capacitor, and the error is not required to be accumulated in an ideal calibration method when the error is compared with the auxiliary capacitor, and the error is not required to be accumulated for the high-accuracy calibration method, and the error is compared with the ideal, and the error is not required to be compared when the error is compared with the high-accuracy-bit calibration method. Disclosure of Invention The invention aims to provide a capacitance mismatch calibration method and circuit of a high-precision successive approximation type analog-to-digital converter, which are used for solving the influence and limitation of capacitance mismatch on the precision of a high-precision ADC in the prior art and improving the data conversion rate. The invention provides a capacitance mismatch calibration method of a high-precision successive approximation type analog-digital converter, wherein the analog-digital converter comprises a capacitance array module, a comparator module and a control module, the capacitance array module comprises a P-end capacitance array and an N-end capacitance array, a preset number of LSB repeated capacitances are respectively arranged in high-order section capacitance arrays corresponding to the P-end capacitance array and the N-end capacitance array, and the method is used for calibrating after the analog-digital converter completes single conversion and obtains an output digital code, and specifically c