CN-121984507-A - Multi-chip multichannel ADC chip synchronization method and device

Abstract

The invention discloses a method and a device for synchronizing multiple multi-channel ADC chips, and belongs to the technical field of wireless communication and signal processing. The method comprises the steps of providing homologous and same-phase reference clock signals for multiple ADC chips and an FPGA through multiple output clock PLL chips, establishing independent data processing channels for each ADC in the FPGA, sequentially performing LVDS serial-parallel conversion and data sample point splicing processing, uniformly converting asynchronous data of each ADC chip into the same system clock domain by adopting asynchronous FIFO, and simultaneously reading all the asynchronous FIFO through synchronous control logic to realize synchronous data output. The device adopts a star topology hardware architecture and comprises a reference clock source, a multi-channel clock PLL chip, a plurality of ADC chips and an FPGA main control chip integrating each processing module. The invention solves the problems of clock phase deviation and data sampling asynchronism among multiple ADCs, realizes high-precision synchronization of the phase difference among channels smaller than 0.3ns, and has the advantages of low realization cost, strong system expansibility and good instantaneity.

Inventors

• HU JINLONG
• ZHAO FENG
• SHI YUANJI

Assignees

• 中科南京移动通信与计算创新研究院

Dates

Publication Date

20260505

Application Date

20251204

Claims (9)

1. 1. A method for synchronizing multiple multi-chip multi-channel ADC chips, comprising: providing homologous reference clock signals to a plurality of ADC chips through a reference clock source, and configuring working parameters of each chip; each ADC chip samples the analog signal under the drive of the synchronous clock and outputs high-speed serial data; Establishing an independent data processing path for each ADC chip in an FPGA main control chip, and carrying out serial-parallel conversion and sample point splicing processing on high-speed serial data to obtain asynchronous data; And converting asynchronous data of each ADC into the same system clock domain through an asynchronous FIFO, and realizing synchronous output of multiple pieces of ADC data by adopting synchronous control logic.
2. 2. The method of claim 1, wherein providing the multiple ADC chips with the homologous reference clock signal comprises: providing a high-precision reference clock signal and inputting the high-precision reference clock signal to a multi-path clock PLL chip; Generating multiple paths of synchronous clock signals with the same frequency and phase, and distributing the synchronous clock signals to the FPGA main control unit and the reference clock ports of each ADC chip; and the FPGA executes an SPI configuration program, writes preset working parameters into the multi-channel clock PLL chip and each ADC chip, and completes chip initialization configuration.
3. 3. The method of claim 1, wherein serial-parallel conversion comprises: the FPGA receives LVDS serial data, data clock signals and frame clock signals from each ADC chip; the clock management module receives the data clock signals of the ADCs, invokes independent PLL resources in the FPGA, performs clock locking and phase adjustment operation, and generates a sampling clock after phase optimization; and performing double-edge sampling and serial-parallel conversion operation on the LVDS serial data by using the sampling clock after phase optimization to generate rising-edge parallel data and falling-edge parallel data.
4. 4. A method according to claim 3, wherein the double edge sampling and serial to parallel conversion operations comprise: Invoking IDDR primitives of the FPGA, and respectively sampling serial data at the rising edge and the falling edge of a sampling clock to obtain rising edge bit data and falling edge bit data; The bit data is subjected to serial-to-parallel conversion by using a shift register, and the parallel data is latched by using a frame clock signal, so that 8-bit-wide rising edge parallel data and falling edge parallel data are generated.
5. 5. The method of claim 1, wherein the sample splicing process comprises: receiving a frame clock signal, calling a global clock buffer of the FPGA, and executing clock driving enhancement operation to obtain an enhanced frame clock; under the drive of the frame clock after the enhancement drive, reading multi-path rising edge and falling edge parallel data; And according to the data bit mapping relation, performing data splicing operation to generate multichannel complete bit width sample data of each ADC chip.
6. 6. The method of claim 1, wherein uniformly transitioning to the same system clock domain through an asynchronous FIFO comprises: Configuring independent asynchronous FIFO for each ADC chip, and receiving the multichannel sample data of the chip and the corresponding enhanced driving frame clock; Monitoring the data buffer depths of all asynchronous FIFOs through synchronous control logic under a system clock domain; when the data quantity of all the asynchronous FIFOs reaches a preset threshold value, generating a unified reading enabling signal; and starting all read operations of the asynchronous FIFO, and outputting synchronous multi-piece multi-channel ADC data.
7. 7. The method of claim 1, further comprising the step of parameter configuration: the FPGA sends a configuration command to the multi-channel clock PLL chip through the SPI interface, and the frequency and phase parameters of the output clock are set; the FPGA sends configuration commands to each ADC chip through an SPI interface, and the sampling rate, the data mode and the clock parameters are set; and dynamically adjusting configuration parameters according to the working state of the system, and optimizing the synchronization performance.
8. 8. The method of claim 1, further comprising the step of phase compensating: Receiving synchronously output multi-channel data, and calculating a fixed phase difference between the channel data; executing a digital delay or phase rotation algorithm to complete high-precision phase compensation; and outputting the synchronous data after phase alignment.
9. 9. A multi-chip multi-channel ADC chip synchronizing device for carrying out the method according to any one of claims 1 to 8, comprising: a reference clock source for providing a high precision clock signal; the multi-channel clock PLL chip is connected with the reference clock source and used for generating multi-channel homologous in-phase clock signals; The ADC chips are connected with the multi-channel clock PLL chip, and are used for receiving synchronous clock signals and sampling analog signals; The FPGA main control chip is connected with the multipath clock PLL chip and each ADC chip, and comprises: The clock management module is used for processing the input clock signal and generating a sampling clock and a system processing clock which are optimized in phase; The parameter configuration module is used for configuring a clock PLL chip and an ADC chip through an SPI interface; the plurality of LVDS serial-parallel conversion modules are corresponding to one ADC chip and are used for converting LVDS serial data into parallel data; A plurality of data sample point splicing modules, each module corresponding to one ADC chip and used for splicing the parallel data into sample data with complete bit width; the asynchronous-to-synchronous processing module is used for converting asynchronous data of each ADC chip into the same system clock domain; and the synchronous control module is used for controlling synchronous read-write operation of each asynchronous FIFO.

Description

Multi-chip multichannel ADC chip synchronization method and device Technical Field The invention relates to the technical field of wireless communication, in particular to a method and a device for synchronizing multiple pieces of multichannel ADC chips. Background In a modern high-speed data acquisition system, the AD9653 is widely applied as a high-performance 4-channel, 16-bit and 125MSPS analog-to-digital converter because of the advantages of low cost, low power consumption, small size, usability and the like of a built-in on-chip sample-and-hold circuit. However, the use of multi-slice multi-channel AD9653 presents challenges when simultaneous acquisition of multiple signals is desired. In one aspect, the LVDS high-speed serial data output by the AD9653 is sampled in dependence on a data clock synchronous differential signal (DCO). However, in an actual system, the DCO signal may generate delay due to factors such as differences of hardware circuits, internal wiring of the FPGA, electrical characteristics of different chips, etc., and the delay may seriously affect the timing sequence of sampling the LVDS high-speed serial data, so that burrs occur at sampling points recovered by the FPGA. At present, aiming at the problem that the DCO delay causes the LVDS high-speed serial data sampling to generate burrs, the existing solution is to use an FPGA to finely adjust delay parameters of an LVDS serial high-speed interface so as to realize phase relation adjustment between the DCO and the LVDS data, thereby avoiding the burrs of the data sampling. However, the method is complex in logic realization, and the delay parameters of the FPGA multipath ADC interface are required to be finely set and repeatedly debugged, so that development difficulty and cost are greatly increased. In addition, in practical engineering application, when the multiple AD9653 samples, the multiple reference clock sources have inconsistent frequencies and phases, and delay differences of clock signals in the transmission process can cause non-negligible phase deviation between data collected by the multiple AD9653, which not only reduces accuracy of data processing, but also may cause that the whole data collecting and processing system cannot work normally, especially in application scenarios with extremely high requirement on data synchronism, such as wireless communication base station signal processing, high-precision test and measurement systems, etc., the influence caused by the problems is more remarkable. For the problem of clock phase difference, the prior art generally identifies and adjusts the phase relationship by calculating the phase of the characteristic signal. However, this method limits the versatility and flexibility of data, and is difficult to adapt to various application scenarios. Meanwhile, the characteristic signals are added and calculated, so that the data processing efficiency is reduced, and the requirement of a high-speed data acquisition system on real-time performance cannot be met. Disclosure of Invention The invention aims to provide a method and a device for synchronizing multiple multi-channel ADC chips, which can solve the problems in the prior art. The technical scheme is that the multi-chip multichannel ADC chip synchronization method comprises the following steps: providing homologous reference clock signals to a plurality of ADC chips through a reference clock source, and configuring working parameters of each chip; each ADC chip samples the analog signal under the drive of the synchronous clock and outputs high-speed serial data; Establishing an independent data processing path for each ADC chip in an FPGA main control chip, and carrying out serial-parallel conversion and sample point splicing processing on high-speed serial data to obtain asynchronous data; And converting asynchronous data of each ADC into the same system clock domain through an asynchronous FIFO, and realizing synchronous output of multiple pieces of ADC data by adopting synchronous control logic. Preferably, providing a homogenous reference clock signal to the multi-chip ADC chip comprises: providing a high-precision reference clock signal and inputting the high-precision reference clock signal to a multi-path clock PLL chip; Generating multiple paths of synchronous clock signals with the same frequency and phase, and distributing the synchronous clock signals to the FPGA main control unit and the reference clock ports of each ADC chip; and the FPGA executes an SPI configuration program, writes preset working parameters into the multi-channel clock PLL chip and each ADC chip, and completes chip initialization configuration. Preferably, the serial-parallel conversion includes: the FPGA receives LVDS serial data, data clock signals and frame clock signals from each ADC chip; the clock management module receives the data clock signals of the ADCs, invokes independent PLL resources in the FPGA, performs clock locking and phas