CN-121984511-A - Sample-and-hold readout system and method for ramp analog-to-digital conversion

Abstract

A sample-and-hold readout system and method for ramp analog-to-digital conversion is presented in which an optical array is read out using a sample-and-hold circuit such that each sample is used to charge a sample-and-hold capacitor and during the hold phase is read out using an amplifier driving a ramp analog-to-digital converter. The sample and hold circuit transitions to a tracking phase where the optical array input drives an amplifier that drives a sample and hold capacitor, and then to a sampling phase where the sample and hold capacitor is directly connected to the optical array output.

Inventors

• ZHONG YANG

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260505

Application Date

20230329

Priority Date

20220407

Claims (10)

1. 1. A sample and hold circuit comprising: from the output of the optical array to the input of the sample-and-hold circuit; A Field Effect Transistor (FET), a source of the FET being connected to an output of the sample-and-hold circuit; A first switch electrically coupled to the output of the optical array at one end of the first switch and electrically coupled to a common point at the other end of the first switch; A second switch electrically coupled to the common point at one end of the second switch and electrically coupled to a sample-and-hold capacitor and a gate of the FET at the other end of the second switch; A third switch electrically coupled to the common point at one end of the third switch and electrically coupled to ground at the other end of the third switch.
2. 2. The sample-and-hold circuit of claim 1 wherein the FET further comprises a source follower.
3. 3. The sample-and-hold circuit of claim 1 wherein the FET is biased by a current source.
4. 4. The sample-and-hold circuit of claim 1, wherein the output of the sample-and-hold circuit is electrically coupled to an analog-to-digital converter (ADC).
5. 5. The sample-and-hold circuit of claim 4 wherein the ADC comprises a comparator.
6. 6. The sample-and-hold circuit of claim 5 wherein the ADC further comprises a coupling capacitor having one end electrically coupled to the first input of the comparator and the other end electrically coupled to the output of the amplifier.
7. 7. The sample-and-hold circuit of claim 6 wherein the ADC further comprises a fourth switch for resetting the capacitor.
8. 8. The sample-and-hold circuit of claim 7, wherein the ADC further comprises a ramp generator electrically coupled to a second input of the comparator.
9. 9. The sample-and-hold circuit of claim 8, wherein the ramp generator comprises a digital-to-analog converter (DAC).
10. 10. The sample-and-hold circuit of claim 9 wherein the ramp generator further comprises a counter electrically coupled to a digital input of the DAC.

Description

Sample-and-hold readout system and method for ramp analog-to-digital conversion The application is a divisional application of patent application with the application number 202310323583.0 and the application name of 'sample-and-hold read-out system and method for ramp analog-to-digital conversion' filed on 29 of 2023, 03. Technical Field The present disclosure relates to sample-and-hold readout systems and methods for ramp analog-to-digital conversion, and more particularly to a sample-and-hold circuit and a sample-and-hold method for converting an optical array sample to a digital representation. Background The optical sensor is composed of cells or pixels that store the amount of charge determined by the exposure. An image is formed of an array of pixels exposed to light from a scene. In order to read the generated image, the charge stored on the pixel array needs to be read out. A common approach is to sample each pixel by allowing it to charge a device such as a capacitor and then converting the voltage of the capacitor using an analog-to-digital converter or ADC. A common technique for converting from analog to digital is to use a ramp ADC. The ramp ADC is an ADC that supplies the voltage to be converted to the input of the comparator. The other comparator input is fed by a digital-to-analog converter, which is digitally driven by a counter. The counter counts until the comparator trips. When the comparator trips, the counter is stopped and the value of the counter is saved as a digital equivalent representation of the converted voltage. A simplified representation of this system is shown in fig. 1. FIG. 1 is a prior art block diagram of optical array sensing and readout electronics. It shows the optical array output electrically coupled to sample and hold circuit 120. The sample and hold circuit is electrically coupled to a comparator (comp). The comparator also has an input electrically coupled to a ramp buffer (ramp_buf), a buffered output of a digital-to-analog converter (not shown). When the comparator triggers (the two inputs are equal), the value of the counter driving the digital to analog converter is stored in a memory (ASRAM). The comparator capacitor 110 is discharged or reset by assertion (assertion) of a control called Dcpmp _rst. Fig. 2 is a schematic diagram of the sample-and-hold circuit of fig. 1. Fig. 2 shows two identical branch circuits so that the pixels can be read and converted in a pipelined fashion. Fig. 3 is a timing diagram of the circuit of fig. 2, useful for understanding the sample and hold process that occurs in the sample and hold circuit. The sequence starts with closing sw1, opening sw2 (T1) so that only the upper half of the circuit is connected to the input. At time T1, rst2 is also asserted. The capacitor 210 is connected to Vin via a switch shr1 to sample the reset value (R1) of row 1. The charge remains in the capacitor 210 until the charge is read out and converted. Switch shr1 is opened and then shr1 is closed at (T2), connecting 212 to input Vin to sample the signal value (S1) of row 1. When sw1 is off (T3), the two capacitors 210 and 212 connected to shr1 and shr1 hold the pixel reset sum signal of row 1. The ADC conversion for row 1 pixels starts with an rst1 pulse (T4) to clear the sampling node in the top branch. Also at T4, sw2 is closed and sampling of R (2) is started. In the source follower configuration, shr is again closed to connect the capacitor 210 to the gate of FET Q220. The reset value is held and converted by counting the digital inputs to the DAC. When the output of the DAC equals the sample value, the pixel value is stored. The opposite is true for the bottom circuit connected to sw 2. When S1 is closed, S2 is open, and 214 and 216 are in their respective hold states, the samples taken during the previous sampling phase are transitioned, as indicated by the countdown R0 and the countup S0. When s1 is open, s2 is closed (T3) and the next two pixels are sampled. Following the same readout sequence for the pixel signal, starting with the rst1 pulse (T5) to clear the sampling node in the top branch. The shs2 switch (T6) is closed to connect the capacitor 212 to the source follower Q220. The upper and lower circuits, each driving their respective transistors 220 and 222 in turn, are each configured to drive a source follower of the output. Thus, two circuits connected to sw1 and sw2 perform sampling and holding in such a manner that one circuit samples and the other circuit holds and reads out the result. Each having a respective source follower capable of driving an output. The foregoing example shows two sample-and-hold branches, each with one sample-and-hold capacitor for the shr signal and one sample-and-hold capacitor for the shr signal. The two sample-and-hold branches operate in a pipelined mode, one branch sampling the signal of one channel and the other branch outputting the signal of the other channel to the ADC for conversion. The dis