CN-121984513-A - Quantizer, modulator and signal processing method

CN121984513ACN 121984513 ACN121984513 ACN 121984513ACN-121984513-A

Abstract

The application provides a quantizer, a modulator and a signal processing method, which are suitable for the technical field of integrated circuits. The quantizer comprises a signal processing circuit, a comparison circuit and a logic control circuit, wherein the logic control circuit is electrically connected with the signal processing circuit and the comparison circuit, the logic control circuit is configured to control the signal processing circuit to increase the difference value between the second differential signal and the first differential signal by a preset voltage to form a first group of target input signals to be output to the comparison circuit, and the signal processing circuit is controlled to perform successive approximation type quantization operation on one group of differential input signals based on preset logic control information and digital output codes output by each comparison circuit, so that the quantizer can finish a middle-pedal type quantization curve. The embodiment of the application changes the successive approximation type quantization logic mode of the quantizer through the logic control circuit, widens the application scene of the quantizer, and has wide market application prospect.

Inventors

LU YULING
CHEN MENGBANG
CAI RONGHUAI
CHEN JINYI

Assignees

宗仁科技(平潭)股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251230

Claims (10)

1. A quantizer of the data of a video signal, characterized by comprising the following steps: A signal processing circuit configured to sequentially output a plurality of sets of target input signals based on a set of differential input signals, the set of differential input signals including a first differential signal and a second differential signal; The comparison circuit is electrically connected with the signal processing circuit and is configured to compare each group of target input signals to sequentially obtain a plurality of digital output codes; The logic control circuit is electrically connected with the signal processing circuit and the comparison circuit and is configured to control the signal processing circuit to increase the difference value of the second differential signal and the first differential signal by a preset voltage to form a first group of target input signals to be output to the comparison circuit, and based on preset logic control information and digital output codes output by each comparison circuit, the logic control circuit is controlled to perform successive approximation type quantization operation on one group of differential input signals and sequentially output the rest groups of target input signals so as to enable the quantizer to finish a middle-pedal type quantization curve, wherein the middle-pedal type quantization curve represents digital zero level output.
2. The quantizer of claim 1 wherein the comparison circuit comprises a comparator and the signal processing circuit comprises a sampling circuit, a signal translation circuit, and at least two charge-discharge circuits; the first output end and the second output end of the sampling circuit are respectively and electrically connected with the in-phase input end and the anti-phase input end of the comparator, and the sampling circuit is configured to sample the first differential signal and the second differential signal in a sampling period and output the first differential signal and the second differential signal to the comparator through the first output end and the second output end of the sampling circuit respectively; the first output end and the second output end of the signal translation circuit are respectively and electrically connected with the in-phase input end and the anti-phase input end of the comparator, and the signal translation circuit is configured to output a group of reference signals to the comparator in a quantization period so as to increase the difference value of the second differential signal and the first differential signal by a preset voltage to form a first group of target input signals; The first output end and the second output end of each charge-discharge circuit are respectively and electrically connected with the non-inverting input end and the inverting input end of the comparator, and each charge-discharge circuit is configured to output a group of reference signals to the comparator in a quantization period so as to perform successive approximation type quantization operation on a group of differential input signals.
3. The quantizer of claim 2 wherein the sampling circuit comprises a first switching device, a second switching device, a third switching device, a fourth switching device, a fifth switching device, a sixth switching device, a first sampling capacitance, and a second sampling capacitance; The first end of the first sampling capacitor is electrically connected with the first switching device and the second switching device, the second end of the first sampling capacitor is electrically connected with the first output end of the sampling circuit and the fifth switching device, the first switching device is electrically connected with the input end of the first differential signal, and the second switching device and the fifth switching device are grounded; The first end of the second sampling capacitor is electrically connected with the third switching device and the fourth switching device, the second end of the second sampling capacitor is electrically connected with the second output end of the sampling circuit and the sixth switching device, the fourth switching device is electrically connected with the input end of the second differential signal, and the third switching device and the sixth switching device are grounded.
4. The quantizer of claim 3 wherein said logic control circuit is configured to control said first, fourth, fifth and sixth switching devices to be on during a sampling period to cause said first and second sampling capacitances to sample said first and second differential signals, respectively, and to control said first, fourth, fifth and sixth switching devices to be off during a quantization period to cause said second and third switching devices to be on.
5. The quantizer of claim 2 wherein the signal translation circuit comprises a seventh switching device, an eighth switching device, a ninth switching device, a tenth switching device, a first redundancy capacitor, and a second redundancy capacitor; the first end of the first redundant capacitor is electrically connected with the seventh switching device and the eighth switching device respectively, the second end of the first redundant capacitor is used as a first output end of the signal translation circuit, the seventh switching device is grounded, and the eighth switching device is electrically connected with the input end of the first reference signal; The first end of the second redundant capacitor is electrically connected with the ninth switching device and the tenth switching device respectively, the second end of the second redundant capacitor is used as the second output end of the signal translation circuit, the ninth switching device is grounded, and the tenth switching device is electrically connected with the input end of the second reference signal.
6. The quantizer of claim 5 wherein said digital output code is 0 or 1, said digital output code being 0 corresponding to an input signal at said non-inverting input being less than an input signal at said inverting input, said digital output code being 1 corresponding to an input signal at said non-inverting input being greater than an input signal at said inverting input; The logic control circuit is configured to control the eighth switching device and the tenth switching device to be turned on during a quantization period to output a set of the reference signals to the comparators, respectively, and to control the eighth switching device and the tenth switching device to be turned off to generate a final set of target input signals if all the digital output codes are 1 at the time of the last comparison by the comparators.
7. The quantizer according to claim 2, wherein each of the charge-discharge circuits includes an eleventh switching device, a twelfth switching device, a thirteenth switching device, a fourteenth switching device, a fifteenth switching device, a sixteenth switching device, and two charge-discharge capacitances of the same capacitance, the two charge-discharge capacitances being a first charge-discharge capacitance and a second charge-discharge capacitance, respectively; The first end of the first charge-discharge capacitor is electrically connected with the eleventh switching device, the twelfth switching device and the thirteenth switching device, and the second end of the second charge-discharge capacitor is used as a first output end of the charge-discharge circuit; The first end of the second charge-discharge capacitor is electrically connected with the fourteenth switching device, the fifteenth switching device and the sixteenth switching device, and the second end of the second charge-discharge capacitor is used as a second output end of the charge-discharge circuit; the charge and discharge capacitors of the charge and discharge circuits are sequentially arranged according to preset capacitance which is 2 M times, M is more than or equal to 0, and M is an integer.
8. The quantizer according to claim 7, wherein said logic control circuit is configured to sequentially control one of said charge-discharge circuits to charge and discharge said comparator's non-inverting input terminal and inverting input terminal to generate a next set of target input signals when said comparator outputs each digital output code in order of increasing capacitance of each of said charge-discharge capacitors, to control said twelve switching devices and said fifteen switching devices to be turned on when said digital output code is 1 and to control said thirteen switching devices and said sixteen switching devices to be turned on when said digital output code is 0, and to control said digital output code to be 0 when said digital output code is 0 and said non-inverting input terminal to be smaller than said inverting input terminal, and to control said digital output code to be 1 when said digital output code is 1 and said non-inverting input terminal to be larger than said inverting input terminal.
9. A modulator comprising a quantizer as claimed in any one of claims 1-8.
10. A signal processing method applied to a quantizer according to any of claims 1-9, said method comprising: The control signal processing circuit increases the difference value of the second differential signal and the first differential signal by a preset voltage to form a first group of target input signals and outputs the first group of target input signals to the comparison circuit; Based on preset logic control information and digital output codes output by each comparison circuit, the signal processing circuit is controlled to perform successive approximation type quantization operation on one group of differential input signals, and other groups of target input signals are sequentially output so that the quantizer can finish a pedal type quantization curve, wherein the pedal type quantization curve represents digital zero level output.

Description

Quantizer, modulator and signal processing method Technical Field The application relates to the technical field of integrated circuits, in particular to a middle-pedal successive approximation type quantizer, a modulator and a signal processing method. Background With the rapid development of the emerging fields of the internet of things, wearable devices, portable medical devices and the like, the design of low power consumption (for example, a Delta-Sigma modulator) has become one of the core challenges in the field of mixed signal integrated circuits. The traditional modulator is difficult to balance between high precision and low power consumption, particularly in 5G communication, intelligent sensors and edge computing nodes, the system needs to realize high-fidelity acquisition of weak signals in a complex electromagnetic environment, and meanwhile, the severe requirements of millimeter-level chip area and microwatt-level power consumption are met, so that the energy efficiency ratio of the modulator is provided with higher standards. Quantizer as an important part of the modulator, the design of the quantizer is critical. For example, successive approximation SAR quantizers are widely used because of their friendliness to process scaling. However, the conventional successive approximation type quantizer based on the dichotomy can only realize a medium-rise quantization curve, which causes that the digital output of the quantizer cannot carry out multiplication and division operation on the digital output along a common mode, and further causes that the application of the modulator is limited, and the development process of low power consumption of the modulator is limited. Disclosure of Invention In view of the above, the embodiments of the present application provide a quantizer, a modulator and a signal processing method, so as to solve the problem that the application of the modulator is limited because the conventional successive approximation quantizer can only implement a medium-rising quantization curve in the prior art. An embodiment of the present application provides a quantizer including: A signal processing circuit configured to sequentially output a plurality of sets of target input signals based on a set of differential input signals, the set of differential input signals including a first differential signal and a second differential signal; the comparison circuit is electrically connected with the signal processing circuit and is configured to compare each group of target input signals to sequentially obtain a plurality of digital output codes; The logic control circuit is electrically connected with the signal processing circuit and the comparison circuit and is configured to control the signal processing circuit to increase the difference value of the second differential signal and the first differential signal by a preset voltage to form a first group of target input signals to be output to the comparison circuit, and based on preset logic control information and digital output codes output by each comparison circuit, the logic control circuit is used for performing successive approximation type quantization operation on one group of differential input signals and sequentially outputting the rest groups of target input signals so as to enable the quantizer to finish a middle-pedal type quantization curve, wherein the middle-pedal type quantization curve represents digital zero level output. In one possible implementation, the comparison circuit includes a comparator, and the signal processing circuit includes a sampling circuit, a signal translation circuit, and at least two charge-discharge circuits; the first output end and the second output end of the sampling circuit are respectively and electrically connected with the in-phase input end and the anti-phase input end of the comparator, and the sampling circuit is configured to sample the first differential signal and the second differential signal in a sampling period and output the first differential signal and the second differential signal to the comparator through the first output end and the second output end of the sampling circuit respectively; The first output end and the second output end of the signal translation circuit are respectively and electrically connected with the non-inverting input end and the inverting input end of the comparator, and the signal translation circuit is configured to output a group of reference signals to the comparator in a quantization period so as to increase the difference value between the second differential signal and the first differential signal by a preset voltage to form a first group of target input signals; The first output end and the second output end of each charge-discharge circuit are respectively and electrically connected with the non-inverting input end and the inverting input end of the comparator, and each charge-discharge circuit is configured to output a group of ref