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CN-121984521-A - Multi-LDPC codeword joint verification method based on partial extra verification

CN121984521ACN 121984521 ACN121984521 ACN 121984521ACN-121984521-A

Abstract

The invention provides a multi-LDPC code word joint check method based on partial extra check, belonging to the field of flash error correction coding, which aims to solve the problems of reduced read-write efficiency caused by mismatching of 16KB LDPC code words and common flash page sizes and overhigh hardware expense of a 16KB coder and decoder, the method realizes the error correction capability close to the 16KB LDPC by improving 4KB LDPC, associates 4KB LDPC code words by selecting bits with specific proportion from each 4KB code word to make two-to-two parity check, the generated extra check bits are stored in the respective flash memory pages and used as information codes to participate in LDPC encoding and decoding, when data are read, the LDPC decoding is firstly carried out respectively, if decoding fails, partial bits are recovered by means of the correctly decoded code words through extra check, and then the LDPC decoding is carried out again, and the flash memory error correction circuit designed based on the method can approach to the 16KB LDPC performance only by a 4KB LDPC encoder and a single-bit parity check circuit, so that the balance between the error correction performance and hardware cost is achieved.

Inventors

  • SHA JIN
  • XU PEIYUAN

Assignees

  • 南京大学

Dates

Publication Date
20260505
Application Date
20260106

Claims (5)

  1. 1. The multi-LDPC codeword joint verification method based on partial extra verification is characterized by comprising the following steps of: Step 1, determining an information code length n, an extra check bit size p extra and an LDPC check bit size p LDPC , determining a proportional relation, and limiting the size of a flash memory page of an application scene, wherein the sum of the information code length n, the extra check bit size p extra and the LDPC check bit size p LDPC does not exceed the size of the flash memory page, namely the information bit and the redundancy bit of the flash memory page. The proportion selection of the three is limited by the size of the flash memory page, and meanwhile, the error correction performance needs to be determined by considering the actual application scene. The larger the proportion p extra /n of the extra check bit to the information code is, the stronger the error correction performance is, but the occupied bit number is increased, otherwise, the smaller the proportion of the extra check bit to the information bit is, the weaker the error correction performance is, but the storage space is saved. And step 2, respectively taking out the four information codes to be subjected to additional checking, and performing parity checking by combining two information codes to generate four additional checking blocks. And 3, executing the four extra checks obtained in the step 2, adding the four extra checks into the original four information codes one by one, and respectively performing 4KB LDPC coding as information bits integrally to obtain data finally stored in 4 flash memory pages. And 4, reading data from the flash memory page and starting decoding. Firstly, 4KB LDPC decoding is carried out, if decoding fails, the other three pages of data with additional check relation are taken out, 4KB LDPC decoding is carried out, only one of the 4 pages can be successfully decoded, other error pages can recover partial data by means of the additional check of the page, and then LDPC decoding is carried out based on partial correct bits, so that the probability of successful decoding is greatly improved.
  2. 2. The method according to claim 1, wherein in step 2, the portion to be additionally checked is denoted as a row vector c m having a size of 1 xp extra , and is obtained by the following expression: c m ＝k m ×A sel ,m=1,2,3,4 (1) Wherein k m represents an mth information code, and is represented by a row vector of 1×n, and m takes values of 1, 2, 3 and 4: k m ＝[k m1 k mz … k mn ],m=1,2,3,4 (2) A sel is a matrix with the size of n multiplied by p extra of the screened partial check area, and after the matrix multiplication is completed, an extra check row vector c m is obtained. The 4 information codes respectively correspond to c 1 、c 2 、c 3 、c 4 , and parity check is carried out by combining two information codes:
  3. 3. The method of claim 1, wherein in step 3, the original information code k m and the generated extra check code p extram are combined to obtain the information bits used for LDPC encoding by using the following formula: k LDPCm ＝[k m p extram ],m=1,2,3,4 (4) The final full LDPC codeword is: c LDPCm ＝[k m p extram p LDPCm ],m=1,2,3,4 (5) The extra check code needs to be protected by an LDPC error correction mechanism, otherwise, the correctness of the read extra check bit cannot be ensured, and the extra check mechanism is in error.
  4. 4. The method of claim 1, wherein in step 4, after the correct extra check bits are obtained from the error codeword, a log likelihood ratio posterior probability information (LLR) immobilization operation is performed on the corrected bits for the LDPC decoder: The LLR is fixed to a positive maximum value corresponding to a bit with a value of 0, the LLR is fixed to a negative maximum value corresponding to a bit with a value of 1, and LLR information of the bit is kept unchanged in the following decoding process. The correct bit LLR information is fixed, and then the correct code word information can be effectively transferred to other bits to be corrected by means of a message transfer mechanism in the LDPC decoding process, so that the aim of auxiliary decoding is fulfilled, and the success probability of repeated decoding is improved.
  5. 5. A storage medium storing a computer program or instructions which, when run on a computer, performs the steps of the method of any one of claims 1 to 4.

Description

Multi-LDPC codeword joint verification method based on partial extra verification Technical Field The invention belongs to the field of flash memory error correction coding. Background A Low-Density Parity-Check (LDPC) is a linear block code with a sparse Check matrix, and is characterized in that the number of zero elements in the Check matrix is far greater than that of non-zero elements. LDPC usually adopts a belief propagation algorithm (Belief Propagation Algorithm) based on soft information to realize decoding through multiple iterations, and the maximum posterior probability of each code element of the code word is obtained in the iterations, so that the correct code word is approximated gradually. The method can realize the error correction performance approaching the Shannon limit under the condition of long codes. The LDPC code with the random construction check matrix has the best performance, but the encoder and the decoder are too complex, so the Quasi-cyclic LDPC (quick-CYCLE LDPC) is invented, and the balance of error correction performance and hardware complexity is obtained by introducing a cyclic shift sub-matrix into the check matrix, so that the LDPC code has been widely applied at present. The LDPC code becomes a core error correction scheme of the present high density flash memory by virtue of its excellent long code error correction performance and acceptable hardware overhead. Flash memory (Flash) is a non-volatile memory that can retain data after power failure, and NAND FLASH has become a mainstream because of its high density and low cost. However, with the shrinking of the Flash process and the increasing of the storage density, the conditions of interference between cells, charge leakage, read-write disturbance and the like are all significantly increased, resulting in frequent errors such as bit flipping. The original 2KB code length LDPC can not meet the requirement of the enterprise SSD on the data reliability, the 4KB LDPC code is the current mainstream, and 16KB LDPC codes with longer code length are needed in the future to achieve higher error correction capability. However, the hardware overhead of the 16KB LDPC is too large, and the mismatch problem exists between the 16KB code length and the current common 4KB flash memory page size, which leads to the reduction of the read-write efficiency. Disclosure of Invention The invention aims to: the invention aims to solve the technical problems of excessive hardware cost and mismatch with the common flash memory page size of 16KB LDPC, and provides a multi-LDPC code word joint checking method based on the extra checking of a 4KB LDPC combined part, by respectively dividing bit areas with certain sizes from 4KB LDPC code words, and extra parity check is carried out between every two of the two, so that partial data can be recovered from correctly decoded codewords in the 4 codewords, and LDPC decoding is carried out again, thus the error correction performance can be greatly improved by using only 4KB LDPC plus a simple parity check circuit and using smaller hardware cost, and the size of a flash memory page of 4KB can be adapted. The method comprises the following steps: Step 1, determining an information code length n, an extra check bit size p extra and an LDPC check bit size p LDPC, determining a proportional relation, and limiting the size of a flash memory page of an application scene, wherein the sum of the information code length n, the extra check bit size p extra and the LDPC check bit size p LDPC does not exceed the size of the flash memory page, namely the information bit and the redundancy bit of the flash memory page. The proportion selection of the three is limited by the size of the flash memory page, and meanwhile, the error correction performance needs to be determined by considering the actual application scene. The larger the proportion p extra/n of the extra check bit to the information code is, the stronger the error correction performance is, but the occupied bit number is increased, otherwise, the smaller the proportion of the extra check bit to the information bit is, the weaker the error correction performance is, but the storage space is saved. And step 2, respectively taking out the four information codes to be subjected to additional checking, and performing parity checking by combining two information codes to generate four additional checking blocks. And 3, adding four extra checks into the original four information codes one by one, and respectively performing 4KB LDPC coding as information bits integrally to obtain data finally stored in 4 flash memory pages. And 4, reading data from the flash memory page and starting decoding. Firstly, 4KB LDPC decoding is carried out, if decoding fails, the other three pages of data with additional check relation are taken out, 4KB LDPC decoding is carried out, as long as one of the 4 pages can be successfully decoded, other error pages can recover part of dat