CN-121984522-A - LDPC input data circuit

Abstract

The invention discloses an LDPC input data circuit, and relates to the field of channel decoding. The circuit comprises an input buffer module, a code word buffer module, a repeated data buffer module and a control module, wherein the input buffer module is used for buffering input data from a preceding module with a preset data bit width, the code word buffer module comprises at least two code word buffers and is used for alternately storing LDPC code word data to be decoded, the repeated data buffer module is used for buffering load data marked as needing to be repeatedly processed in a data filling stage, the control module is used for controlling the data to be in a configurable parallel bit width, reading the data from the input buffer module and/or the repeated data buffer module according to a preset filling state sequence, carrying out parallel bit width processing on the input data according to shorten, puncture or repeat processing modes corresponding to current data, and writing the processed data into the code word buffer in a writing state in the code word buffer module. The invention improves the processing efficiency of LDPC iterative decoding.

Inventors

• YANG JIANMING
• HONG HAO
• LIU HAO
• ZHANG JING

Assignees

• 珠海泰芯半导体有限公司

Dates

Publication Date

20260505

Application Date

20260112

Claims (10)

1. 1. An LDPC input data circuit, comprising: the input buffer module is used for buffering the input data from the front-stage module with a preset data bit width; The code word buffer module comprises at least two code word buffer areas and is used for alternately storing LDPC code word data to be decoded; the repeated data caching module is used for caching the load data marked as needing repeated processing in a data filling stage; The control module is used for controlling the data to be in a configurable parallel bit width, reading the data from the input buffer module and/or the repeated data buffer module according to a preset filling state sequence, carrying out parallel bit width processing on the input data according to shorten, puncture or repeat processing modes corresponding to the current data, and writing the processed data into a codeword buffer in a writing state in the codeword buffer module.
2. 2. The LDPC input data circuit of claim 1, wherein the codeword buffer module comprises a first codeword buffer and a second codeword buffer, the control module configured to: When the first codeword buffer is in a state of being read by an LDPC decoding circuit for iterative decoding, the control module controls data to be written into the second codeword buffer; The control module controls data writing into the first codeword buffer when the second codeword buffer is in a state of being read by the LDPC decoding circuit.
3. 3. The LDPC input data circuit of claim 1, wherein when the current data corresponds to a repeat mode, the control module is configured to write the current input data from the input buffer module to a corresponding location of the codeword buffer module after performing an operation on the current input data and the payload data buffered in the repeat data buffer module.
4. 4. An LDPC input data circuit according to claim 3, wherein the control module operates on current input data from the input buffer module and load data buffered in the repeat data buffer module, including a weighted average operation or an arithmetic average operation.
5. 5. The LDPC input data circuit of claim 1, wherein when the current data corresponds to shorten modes, the control module inserts preset shorten bits into the codeword buffer module when the input data does not reach a target LDPC codeword length, so that an information bit length of the input data satisfies the target LDPC codeword length.
6. 6. The LDPC input data circuit of claim 1, wherein the control module controls padding the codeword buffer module with predetermined padding bits to pad to a target LDPC codeword length when the current data corresponds to puncture modes and when a data length in the codeword buffer module is less than the target LDPC codeword length.
7. 7. The LDPC input data circuit according to claim 1, wherein the input buffer module and the control module are configured to process multi-bit data in parallel according to an actual bit width of the input data in each clock cycle, wherein the configurable parallel bit width is selected from one of 1 bit, 2 bits, 4 bits, 6 bits, 8 bits, 10 bits or 12 bits, the parallel bit width matching a symbol bit width of the output of the front-stage demodulator.
8. 8. An LDPC input data circuit processing method applied to the LDPC input data circuit of any one of claims 1 to 7, comprising: acquiring input data from a front-stage module, and caching according to the bit width of the input data; Judging a processing mode corresponding to the input data according to the length of the LDPC code word, wherein the processing mode comprises shorten, puncture or repeat; according to the processing mode, performing filling, discarding or repeating operation processing on the input data; and writing the processed data into a codeword buffer module so that the information bit length of the input data meets the target LDPC codeword length.
9. 9. The LDPC input data circuit processing method of claim 8, wherein the LDPC input data circuit processing method is implemented by a state machine, the state machine comprising at least: A payload fill state, shorten fill state, a parity fill state, a repeat fill state, and a puncture fill state.
10. 10. A communication device comprising a demodulator, an LDPC decoder, and an LDPC input data circuit as claimed in any one of claims 1 to 7; The demodulator is used for outputting soft information data streams with configurable parallel bit width organization to an input buffer module of the LDPC input data circuit; the LDPC decoder is used for reading the complete preprocessed code word from the code word buffer module of the LDPC input data circuit to perform iterative decoding.

Description

LDPC input data circuit Technical Field The invention relates to the technical field of channel decoding, in particular to an LDPC input data circuit. Background The LDPC needs to iterate to decode correct data, and the payload data segment in WIFI adopts channel coding of LDPC, and in this process, the LDPC iterative decoding needs to be performed by changing the data into the size of LDPC codeword specified in WIFI protocol, for example, the size of codeword specified in WIFI protocol is 648/1296/1944, so that the input data is divided into the above 3 lengths to trigger the LDPC decoding. To address the case of code length alignment in LDPC (alignment 648/1296/1944), then the shorten/punturn/repeat case in WIFI needs to be addressed. The conventional LDPC decoding input circuit generally adopts a first-in first-out (FIFO) buffer area to process data, the data is processed in a bit-by-bit (1 bit/period) sequential mode, and the specific flow is that the received data is cached in the FIFO, payload data is read bit by bit, shortening bits (shorten bits) are inserted, parity bits (parity bits) are processed, and for the repetition case, data average operation is required. The main disadvantage of the prior art is the low processing efficiency. For example, when processing a codeword containing 1234-bit payload, 386-bit shorten, 324-bit parity and 2-bit repeat, only 1-bit data can be processed per clock cycle, requiring a total of 1946 clock cycles to complete the pre-processing of a codeword. This inefficient processing method severely occupies the time resources of the subsequent LDPC iterative decoding, and may cause that the overall decoding speed cannot meet the real-time communication requirement. Disclosure of Invention The embodiment of the invention provides an LDPC input data circuit which can solve the technical problem of low LDPC iterative decoding processing efficiency in the prior art. The technical scheme is as follows: in a first aspect, an embodiment of the present invention provides an LDPC input data circuit, including: the input buffer module is used for buffering the input data from the front-stage module with a preset data bit width; The code word buffer module comprises at least two code word buffer areas and is used for alternately storing LDPC code word data to be decoded; the repeated data caching module is used for caching the load data marked as needing repeated processing in a data filling stage; The control module is used for controlling the data to be in a configurable parallel bit width, reading the data from the input buffer module and/or the repeated data buffer module according to a preset filling state sequence, carrying out parallel bit width processing on the input data according to shorten, puncture or repeat processing modes corresponding to the current data, and writing the processed data into a codeword buffer in a writing state in the codeword buffer module. In some embodiments of the invention, the codeword buffer module comprises a first codeword buffer and a second codeword buffer, the control module being configured to: When the first codeword buffer is in a state of being read by an LDPC decoding circuit for iterative decoding, the control module controls data to be written into the second codeword buffer; The control module controls data writing into the first codeword buffer when the second codeword buffer is in a state of being read by the LDPC decoding circuit. In some embodiments of the present invention, when the current data corresponds to the repeat mode, the control module is configured to perform an operation on the current input data from the input buffer module and the payload data buffered in the repeat data buffer module, and then write the current input data into a corresponding position of the codeword buffer module. In some embodiments of the present invention, the control module performs operations on current input data from the input buffer module and the load data buffered in the duplicate data buffer module, including a weighted average operation or an arithmetic average operation. In some embodiments of the present invention, when the current data corresponds to shorten modes, the control module inserts preset shorten bits into the codeword buffer module when the input data does not reach the target LDPC codeword length, so that the information bit length of the input data satisfies the target LDPC codeword length. In some embodiments of the present invention, when the current data corresponds to puncture modes and when the data length in the codeword buffer module is less than the target LDPC codeword length, the control module controls filling a predetermined padding bit into the codeword buffer module to pad to the target LDPC codeword length. In some embodiments of the present invention, the input buffer module and the control module are configured to process multi-bit data in parallel according to an actual bit width of the input dat