CN-121984802-A - Expansion bus system for programmable logic controller expansion

CN121984802ACN 121984802 ACN121984802 ACN 121984802ACN-121984802-A

Abstract

The invention aims to disclose an expansion bus system for expanding a programmable logic controller, which relates to the technical field of signal transmission and comprises a master station module and at least one slave station module, wherein the master station module and each slave station module are sequentially cascaded to form a closed annular data link, the annular data link forms an expansion bus, the expansion bus adopts a differential high-speed physical layer and LVDS transceiver circuits arranged in the master station module and each slave station module, the master station module comprises a master control processor and a master station programmable logic device, and the master station programmable logic device comprises an expansion bus transmitting interface and an expansion bus receiving interface which are used for connecting the expansion bus. The invention has obviously improved communication efficiency, anti-interference capability, instantaneity and system expansibility, and can meet the requirement of a modern industrial control system on a high-performance expansion link.

Inventors

NIE PENGJU
XIE ZHOUYUE
ZHANG YUN
CHEN SHISHUANG

Assignees

深圳市科力尔工业自动化控制技术有限公司

Dates

Publication Date: 20260505
Application Date: 20260119

Claims (9)

1. An expansion bus system for programmable logic controller expansion, comprising: A master station module; at least one slave module; The master station module and each station module are sequentially cascaded to form a closed annular data link, and the annular data link forms an expansion bus; The expansion bus adopts a differential high-speed physical layer, and the differential high-speed physical layer comprises a plurality of pairs of signal lines for transmitting LVDS differential signals and LVDS transceiver circuits arranged in a master station module and each slave station module; the master station module comprises a master control processor and a master station programmable logic device, the master control processor is connected with the master station programmable logic device, and the master station programmable logic device comprises an expansion bus transmitting interface and an expansion bus receiving interface which are used for connecting an expansion bus; Each secondary station module comprises a secondary station programmable logic device, an expansion bus input port circuit and an expansion bus output port circuit, wherein the expansion bus input port circuit is connected with the expansion bus output port circuit of the front-stage module, the expansion bus output port circuit is connected with the expansion bus input port circuit of the rear-stage module, and the expansion bus input port circuit and the expansion bus output port circuit are respectively connected with the secondary station programmable logic device of the secondary station module and are used for forwarding LVDS differential signals between the modules; The master station programmable logic device and each slave station programmable logic device are internally provided with a clock data recovery circuit, an 8b/10b encoding and decoding circuit and a CRC check circuit, wherein the 8b/10b encoding and decoding circuit is used for carrying out 8b/10b encoding and decoding on a message frame transmitted on an expansion bus, and the CRC check circuit is used for generating and checking a CRC check field in the message frame; The master station programmable logic device is configured to inject a single-frame message on the expansion bus, so that the single-frame message sequentially passes through all the slave station modules along the annular data link and returns to the master station module to form a single-message large loop; each slave programmable logic device is configured to perform read-write operation on a data field corresponding to the slave station module in a message frame under the condition of not interrupting continuous transmission of a single-frame message when the single-frame message passes through the slave station module, and continuously send the updated message frame to the slave station module at the later stage, thereby realizing data exchange between the master station module and all the slave station modules.
2. The system of claim 1, wherein the master programmable logic device first transmits a basic message frame for link initialization after the system is powered on, the basic message frame at least comprises a frame type field, a station number field, a frame length field and a plurality of basic register fields, each slave programmable logic device is configured to add 1 to the current value of the station number field as the station number of the slave when receiving the basic message frame, write the updated station number field back to the basic message frame and then forward the updated station number field to a later slave module, and the master programmable logic device takes the final value in the station number field as the number of the slave modules when receiving the basic message frame which is sequentially processed by each slave module, thereby completing self-detection of the number of the slave modules.
3. The system of claim 2 wherein the master programmable logic device, after completing configuration of all the slave module configuration data by transmitting the configuration frame, transmits a functional message frame on the expansion bus according to a predetermined period, the functional message frame including at least a frame type field, a station number field, a frame length field, a plurality of slave data fields, and a frame tail CRC field, each of the slave programmable logic devices determining a slave data field corresponding to the slave in the functional message frame according to the station number of the slave, reading input data from the slave data field and writing output data to the slave data field when a single frame message passes through the slave.
4. A system as claimed in claim 3, characterized in that an internal dual-port memory DPRAM is provided in each slave module, the slave programmable logic device being bi-directionally connected to the internal dual-port memory DPRAM.
5. The system of claim 4, wherein the slave module includes a microcontroller MCU connected to the internal dual port memory DPRAM, wherein the slave programmable logic device outputs an interrupt signal to the microcontroller MCU upon detection of the broadcast synchronization frame, wherein the microcontroller MCU accesses the internal dual port memory DPRAM via the AHB bus during an interrupt service routine to interact with the master module, and wherein the slave programmable logic device directly drives the input/output channel of the slave module based on data in the internal dual port memory DPRAM upon detection of the broadcast synchronization frame when the slave module does not include the microcontroller MCU.
6. The system of any of claims 1-5, wherein each slave programmable logic device is configured to perform a link alignment operation upon system power-up, comprising controlling the expansion bus output port circuitry of the present module to output a pre-agreed training code on the downlink, the training code being a fixed bit sequence for link initialization and not for transmission of traffic data, and performing clock recovery and character alignment of the received data stream upon receipt of the training code using the clock data recovery circuitry and the 8b/10b codec circuitry.
7. The system of claim 6, wherein each slave programmable logic device is further configured to perform a self-insertion soft detection operation comprising monitoring whether the own module expansion bus input port circuit receives a training code from a slave module of a later stage and completes alignment within a predetermined detection time, determining that the slave module of the later stage is present when the training code is received within the predetermined detection time, determining that the slave module of the later stage is not present when the training code is not received within the predetermined detection time, and determining the own module as a last slave module.
8. The system of claim 7, wherein the expansion bus output port circuit and the expansion bus input port circuit each comprise an LVDS differential pair connected to the connector, a common mode choke disposed on the differential pair, a termination matching resistor connected between the differential pair and the slave programmable logic device, and an electrostatic protection device, the common mode choke configured to suppress common mode interference, the termination matching resistor configured to match a characteristic impedance of the differential pair, the electrostatic protection device configured to enhance an anti-electrostatic shock capability of the port.
9. The system of claim 8, wherein the clock data recovery circuit is configured to extract clock edges from the 8b/10b encoded data signal and reconstruct a local clock to reduce jitter and offset in the link, the 8b/10b codec circuit improves reliability of clock recovery and long distance transmission by ensuring DC balance of the code stream and sufficient code pattern conversion edges, and the CRC check circuit detects burst noise, single bit flip and multi bit errors by calculating and comparing CRC check fields at the end of a message frame and generates a link error flag when the CRC check fails.

Description

Expansion bus system for programmable logic controller expansion Technical Field The present invention relates to the field of signal transmission technologies, and in particular, to an expansion bus system for expanding a programmable logic controller. Background The programmable logic controller is used as core equipment in an industrial automation scene and is usually connected with various input and output devices through an expansion bus so as to realize the functions of collecting external signals and driving an executing mechanism. With the continuous expansion of the scale of an automation system, the number of expansion units is in a rapid growth trend, and the bandwidth, stability and anti-interference capability of an expansion bus serving as a basic communication link for connecting a host with a plurality of input/output nodes directly determine the real-time performance and reliability of the whole control system. For the architecture and implementation of expansion buses, there are long-standing multiple technical routes in the industry, and applications have been obtained in different products, where implementation modes represented by communication dedicated chips, microcontrollers and programmable logic devices are common. In some industrial control systems, the construction of an extended link through a communication-specific chip is an early emerging approach. Fixed link layer protocol and coding logic are preset in the communication special chip, the same devices are respectively deployed on the host side and the extension unit side, and point-to-point communication is carried out through special time sequence and port type. Because the electric interface parameters and the frame format are fixed in the chip, the communication quality is relatively stable, and the method is suitable for realizing a medium-rate serial expansion channel. However, the hardware logic of the communication dedicated chip is generally difficult to change after leaving the factory, and when the system needs to increase a higher data rate, support a new input/output type or adopt a new control strategy, the system cannot be solved through software upgrading, and the chip itself must be replaced, so that the system expansibility is insufficient. In addition, the cost of the communication special chip is generally higher than that of a general device, so that the cost ratio is obviously increased when the communication special chip is extended in a large scale. Another common approach is to use a microcontroller as a core, which is responsible for parsing data from the host, forwarding instructions, and controlling local input and output resources in the extended link. The micro-controller scheme is relatively flexible in realization, and can adjust the communication protocol and the frame structure through software, thereby being suitable for control systems with different scales and different rates. However, the speed of operation of microcontrollers and on-chip interfaces have limitations in physical characteristics, such as difficulty supporting data rates of hundreds of megabits per second or more, and are susceptible to interference in complex electromagnetic environments. Meanwhile, the microcontroller needs to execute a large number of protocol processing tasks such as analysis, verification, scheduling and the like, so that response delay and link jitter are easily caused by load increase in a multi-node system, and the requirements of high-real-time application are difficult to meet. With the development of programmable logic device technology, the programmable logic device is gradually becoming a core device of an expansion bus. Because the programmable logic device has high customizable, the protocol processing logic can be realized in a hardware mode, so that the processing delay is obviously reduced, the parallel processing capacity is increased, and the programmable logic device can flexibly adapt to different topological structures and speed requirements. In some existing systems, a point-to-point differential link is constructed by adopting a programmable logic device, and high anti-interference performance is realized through low-voltage differential signal transmission, so that the mode is good in long-distance wiring and strong electromagnetic environment. However, the point-to-point link structure requires the master station to communicate with each expansion unit one by one, and as the number of expansion units increases, the communication polling period increases and the overall system refresh rate decreases. The point-to-point topology also accumulates clock jitter and electrical offset during link level-by-level transmission, which may cause an increase in bit error rate in a complex environment without advanced data recovery and encoding measures. Disclosure of Invention In view of the above, the main object of the present invention is to provide an expansion bus system for expanding a pr