CN-121984811-A - Variable step length constant modulus algorithm blind equalization method and system based on cyclic redundancy check

CN121984811ACN 121984811 ACN121984811 ACN 121984811ACN-121984811-A

Abstract

The invention provides a variable step length constant modulus algorithm blind equalization method and a system based on cyclic redundancy check, comprising the steps of obtaining a receiving signal sent by a sending end after cyclic redundancy check coding and modulation; initializing equalizer parameters, performing iterative processing, namely performing equalization filtering on the current tap coefficients to obtain output signals, performing symbol judgment and cyclic redundancy check on the output signals to generate check results, dynamically adjusting iteration step length of a constant modulus algorithm according to the check results, namely increasing step length if data are wrong, adopting default step length if the data are correct, updating the tap coefficients based on the adjusted step length and error function of the constant modulus algorithm, and repeating the iteration until all signals are processed and outputting a final equalization sequence. The invention senses the channel state in real time and dynamically adjusts the step length through the checking result, obviously reduces steady-state errors while accelerating the algorithm convergence speed, and improves the adaptability and transmission reliability of the communication system under a time-varying channel.

Inventors

XIN XIANGJUN
LI ZHIPEI
CHANG HUAN
TIAN FENG
Yan Chuanji
SHI HUALEI
ZHANG QI
YAO HAIPENG
GAO RAN
TIAN QINGHUA
WANG FU

Assignees

北京邮电大学
北京理工大学

Dates

Publication Date: 20260505
Application Date: 20251222

Claims (9)

1. The blind equalization method of the variable step length constant modulus algorithm based on the cyclic redundancy check is characterized by comprising the following steps: Acquiring a receiving signal, wherein the receiving signal is transmitted after the sending end carries out cyclic redundancy check coding and modulation on original data; Initializing the tap coefficient of an equalizer and the iteration step length of a constant modulus algorithm; performing an iterative process, the following operations being performed in one iteration: Performing equalization filtering processing on the received signal by using the current tap coefficient to obtain an equalization output signal; symbol judgment is carried out on the balanced output signals to obtain judgment data, cyclic redundancy check is carried out on the judgment data, and a check result is generated; Dynamically adjusting the iteration step length of the constant modulus algorithm according to the verification result, wherein if the verification result indicates that the data is wrong, the iteration step length is increased, and if the verification result indicates that the data is correct, the default iteration step length is used; Updating the tap coefficient of the equalizer based on the dynamically adjusted iteration step length and the constant modulus algorithm error function; And repeating the iterative processing until the equalization processing of all the received signals is completed, and outputting a final equalization signal sequence.
2. The blind equalization method of a variable-step constant modulus algorithm based on cyclic redundancy check according to claim 1, wherein dynamically adjusting the iteration step of the constant modulus algorithm comprises: If the check result indicates data errors, multiplying the iteration step length by a step length control factor larger than 1; And if the verification result indicates that the data are correct, restoring the iteration step length to the default step length value which is originally set.
3. The variable step length constant modulus algorithm blind equalization method based on cyclic redundancy check according to claim 1, wherein the constant modulus algorithm error function satisfies the following formula: ; Wherein, the Represent the first Constant modulus algorithm error value at time; represent the first Equalizing the output signal at the moment; Representing the modulus value of the constant modulus algorithm.
4. The variable-step constant modulus algorithm blind equalization method based on cyclic redundancy check according to claim 3, wherein updating the tap coefficient of the equalizer based on the dynamically adjusted iteration step and the constant modulus algorithm error function is achieved by the following formula: ; Wherein, the 、 Respectively represent the first First, the Tap coefficients at time; Representing the iteration step; represent the first Conjugation of the received signal.
5. The cyclic redundancy check based variable step length constant modulus algorithm blind equalization method according to claim 1, wherein the generator polynomial followed by cyclic redundancy check of the decision data is the same as the generator polynomial used by the transmitting end to perform cyclic redundancy check coding of the original data.
6. The cyclic redundancy check-based blind equalization method of a variable step length constant modulus algorithm according to claim 1, wherein the received signal is generated by the transmitting end based on the following steps: performing cyclic redundancy check coding on the original data to form a coded data block with a fixed length; and mapping the coded data block to a symbol of high-order quadrature amplitude modulation for modulation transmission, wherein the number of bits carried by a single symbol of the high-order quadrature amplitude modulation is matched with the length of the coded data block.
7. The cyclic redundancy check based variable step length constant modulus algorithm blind equalization method according to claim 6, wherein the high order quadrature amplitude modulation is 64QAM, and the encoded data block is a 6-bit data block composed of 3 bits of information bits and 3 bits of check bits.
8. A variable step constant modulus algorithm blind equalization system based on cyclic redundancy check, the system comprising: The sending end is used for performing cyclic redundancy check coding, modulation and sending on the original data; A receiving end, configured to perform a blind equalization method for implementing a variable step constant modulus algorithm based on cyclic redundancy check according to any one of claims 1 to 7.
9. A computer readable storage medium having stored thereon a computer program/instruction which when executed by a processor performs the steps of the method according to any of claims 1 to 7.

Description

Variable step length constant modulus algorithm blind equalization method and system based on cyclic redundancy check Technical Field The invention relates to the technical field of communication, in particular to a variable step length constant modulus algorithm blind equalization method and system based on cyclic redundancy check. Background With the rapid development of communication services such as distance education, intelligent transportation, live video broadcast, 5G electronic commerce and the like, the demands of optical communication networks for bandwidth capacity and transmission quality are increasing. In a complex channel environment, multipath fading, bandwidth limitation and other factors can cause signal distortion, so that intersymbol interference and error code occur at a receiving end, and the communication quality is seriously affected. The adaptive equalization technology is a key means for alleviating the above problems, and the blind equalization technology is paid attention to because the blind equalization technology can effectively save the system overhead without a training sequence. The constant modulus algorithm (Constant Modulus Algorithm, CMA) is used as a classical blind equalization algorithm, and is widely applied in optical communication systems because of its simple structure, easy implementation and stable convergence. However, the traditional CMA algorithm adopts a fixed iteration step length, and the inherent contradiction exists between the convergence speed and the steady-state error, namely the convergence can be accelerated when the step length is larger, but the steady-state error can be increased, and the convergence time can be obviously prolonged when the step length is smaller, and the steady-state error can be reduced. This contradiction makes it difficult to adapt to time-varying channel environments, resulting in reduced system performance under dynamic channel conditions. Meanwhile, cyclic redundancy check (Cyclic redundancy check, CRC) is widely used in communication systems as an efficient error detection technique, and can rapidly identify errors in a data transmission process at a receiving end. Although the CRC technology is mature, the CRC technology is only used as an independent error detection module in the traditional equalization process, is not combined with a parameter updating mechanism of an equalizer, and cannot exert the potential value of the CRC technology on real-time judgment of the channel state. Therefore, how to achieve the convergence speed and steady-state accuracy while maintaining the low complexity advantage of the CMA algorithm breaks through the limitation of the fixed step length on the performance, and becomes a technical problem to be solved in the field. Disclosure of Invention In view of this, the embodiment of the invention provides a variable-step constant modulus algorithm blind equalization method and a system based on cyclic redundancy check, so as to solve the problems that the convergence speed and steady state error are difficult to be compatible due to the fixed iteration step, the adaptability is poor under a time-varying channel, and the performance optimization is limited due to the independence of an error detection module and equalization control in the prior art. In one aspect, the invention provides a variable step length constant modulus algorithm blind equalization method based on cyclic redundancy check, which comprises the following steps: Acquiring a receiving signal, wherein the receiving signal is transmitted after the sending end carries out cyclic redundancy check coding and modulation on original data; Initializing the tap coefficient of an equalizer and the iteration step length of a constant modulus algorithm; performing an iterative process, the following operations being performed in one iteration: Performing equalization filtering processing on the received signal by using the current tap coefficient to obtain an equalization output signal; symbol judgment is carried out on the balanced output signals to obtain judgment data, cyclic redundancy check is carried out on the judgment data, and a check result is generated; Dynamically adjusting the iteration step length of the constant modulus algorithm according to the verification result, wherein if the verification result indicates that the data is wrong, the iteration step length is increased, and if the verification result indicates that the data is correct, the default iteration step length is used; Updating the tap coefficient of the equalizer based on the dynamically adjusted iteration step length and the constant modulus algorithm error function; And repeating the iterative processing until the equalization processing of all the received signals is completed, and outputting a final equalization signal sequence. In some embodiments of the present invention, dynamically adjusting the iteration step of the constant modulus algorithm incl