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CN-121984821-A - Carrier synchronization method and synchronization control device based on FPGA

CN121984821ACN 121984821 ACN121984821 ACN 121984821ACN-121984821-A

Abstract

The invention relates to the technical field of carrier synchronization, in particular to a carrier synchronization method and a synchronization control device based on an FPGA (field programmable gate array). The method comprises three stages of phase preprocessing, phase verification and dynamic synchronization adjustment, wherein the FPGA captures Sync0 signals generated by an EtherCAT distributed clock, the preprocessing stage calibrates Sync0 trigger time to an adjustment effective interval, the verification stage detects and confirms that the phase is stable through ten continuous Sync0 triggers, the dynamic adjustment stage executes phase synchronization and frequency compensation based on the Sync0, and the device comprises an MCU (micro control unit) integrating an ESC (electronic control unit) and the FPGA, and the MCU and the FPGA form a bidirectional link transmission signal through an IO (input/output) interface. According to the invention, the EtherCAT distributed clock compensation technology and the FPGA nanosecond timing control capability are combined, the synchronization precision of Sync0 is up to 20ns, the synchronization stability and anti-interference performance are improved through a three-level adjustment mechanism, the dependence of a single host is eliminated, multi-node cooperation is supported, the problems of low precision, poor stability and limited expandability of the traditional master-slave synchronization method are solved, and the method is suitable for the scenes of multi-axis synchronization control, distributed parallel inversion and the like.

Inventors

  • HU YUYANG
  • GUO ZHIQIANG

Assignees

  • 无锡信捷电气股份有限公司

Dates

Publication Date
20260505
Application Date
20260203

Claims (10)

  1. 1. The carrier synchronization method based on the FPGA is characterized by comprising the following steps of: in the phase preprocessing stage, FPGA continuously captures the trigger signal of the global synchronous signal Sync0 generated by EtherCAT distributed clock mechanism, starts phase preprocessing when the Sync0 is triggered for the first time, judges whether the current Sync0 trigger time t 0 is in the effective adjustment interval of the carrier period, if yes, enters the step (2), if not, carries out preprocessing calibration operation; a phase verification stage, namely continuously capturing the next ten Sync0 trigger signals, judging each Sync0 trigger time one by one, verifying whether the Sync0 trigger time is in the effective adjustment interval, entering the step (3) if all the Sync0 trigger time is met, and returning to the step (1) if any trigger time is not met; And (3) in the dynamic synchronization adjustment stage, the Sync0 is used as a synchronization reference, the phase synchronization operation and the frequency error compensation operation are periodically executed on the carrier, and the EtherCAT distributed clock is calibrated by detecting the deviation of the local clock of each node and the bus reference clock in real time.
  2. 2. The FPGA-based carrier synchronization method and the synchronization control device according to claim 1, wherein the preprocessing calibration operation specifically comprises the steps of calculating a difference value DeltaX between a Count value of a carrier counter corresponding to an arrival time of Sync0 for the first time and a lower limit value F/F f –f·T s of an adjustment effective interval, wherein F is a clock frequency of an FPGA synchronization module, F f is a carrier frequency, T s is a phase fixed delay, uniformly adjusting DeltaX per =DeltaX/64 to be within 64 subsequent carriers, and if DeltaX per has a decimal, adding one in an integral way until T 0 falls into the adjustment effective interval.
  3. 3. The FPGA-based carrier synchronization method of claim 1, wherein the time range of the adjustment active interval is [1/F f –T s ,1/F f ], and the corresponding carrier counter Count0 adjustment active interval is [ F/F f –f·T s ,f/F f ], where t 0 [0 ,1/F f ],Count0 [0,f/F f ]。
  4. 4. The method of carrier synchronization based on FPGA of claim 1, wherein the phase synchronization in step (3) is specifically that, for a first carrier in a current Sync0 period, the FPGA synchronization module delays a time period of T s to generate the carrier after the Sync0 is triggered based on a preset T s fixed delay, so that a start phase of the first carrier is aligned with a Sync0 reference phase, and a T s parameter is configured through a configuration interface of the MCU.
  5. 5. The FPGA-based carrier synchronization method of claim 1, wherein the frequency error compensation operation in step (3) specifically includes: the FPGA frequency detection module compares the actual clock count value of the previous Sync0 period with the theoretical clock count value, and calculates a frequency error delta C; Step B, number of carriers in single Sync0 period n=f f /F Sync0 , where F Sync0 is the frequency of Sync0, N Equally dividing the delta C to the N-1 carriers remained in the current Sync0 period to obtain a basic compensation quantity delta C per = delta C/N-1; And C, accumulating the decimal part of the delta C per by a fixed decimal accumulator, when the accumulated quantity exceeds 1, performing integer compensation on the counter of the current carrier, subtracting the delta C per if the actual clock count value is larger than the theoretical clock count value, and otherwise adding the delta C per .
  6. 6. The FPGA-based synchronous control device is characterized by comprising an MCU and an FPGA which are integrated with an ESC component, wherein the MCU and the FPGA are connected through an IO interface, the MCU side outputs global synchronous signals Sync0 to a synchronous module of the FPGA through the ESC module, the FPGA side transmits dynamically adjusted synchronous carriers to the MCU to form a bidirectional interactive link, the FPGA is used for executing the FPGA-based carrier synchronization method according to any one of claims 1-5, and the ESC component is used for analyzing EtherCAT bus instructions, generating Sync0 signals and calibrating a local system clock through an EtherCAT distributed clock synchronization mechanism.
  7. 7. The synchronous control device based on the FPGA according to claim 6, wherein the IO interface is used for transmitting a global synchronous signal Sync0 and a synchronous carrier generated by the FPGA, and the bidirectional interactive link is used for guaranteeing real-time performance and reliability of signal transmission.
  8. 8. The FPGA-based synchronization control device of claim 6, wherein the FPGA comprises a synchronization module for performing Sync0 acquisition, phase preprocessing, and phase synchronization operations, a carrier generation module for generating a synchronization carrier, and a frequency detection module for performing frequency error calculation and frequency compensation operations.
  9. 9. The FPGA-based synchronization control apparatus of claim 6, wherein the EtherCAT distributed clock performs accurate calibration on a local system clock of the ESC by using a compensation algorithm, so that all nodes of the whole system operate in an approximately uniform clock domain, and synchronization accuracy of the Sync0 signal is up to 20ns.
  10. 10. The FPGA-based synchronization control device of claim 6, wherein the adjustment valid interval is a specific time window in which Sync0 is allowed to trigger in a carrier period, the time range is [1/F f –T s ,1/F f ], the corresponding carrier counter Count0 adjustment valid interval is [ F/F f –f·T s , f/F f ], and T s is a fixed offset delay of carrier phase compared with Sync0 phase after the global synchronization signal Sync0 is triggered.

Description

Carrier synchronization method and synchronization control device based on FPGA Technical Field The invention relates to the technical field of carrier synchronization, in particular to a carrier synchronization method and a synchronization control device based on an FPGA. Background Along with the development of industrial control technology, in the fields of multi-axis synchronous control, distributed parallel inversion and the like, the multi-carrier synchronization performance among inverters running in parallel gradually becomes a key factor for determining the overall running precision and stability of a system. For example, in a distributed parallel inverter system, a high-precision synchronous carrier can effectively inhibit circulation between inverters, thereby improving the overall operation efficiency of the system. In the traditional carrier synchronization method, a master-slave synchronization control mode is adopted, namely one inversion unit in the parallel inverter is used as a master, the other inversion units are all slaves, synchronization signals are generated through the master and sent to all slaves, and each slave performs carrier synchronization based on the received synchronization signals. However, the traditional master-slave synchronization method is highly dependent on the synchronization reference provided by a single host, once the host fails or the output is abnormal, the slave immediately loses synchronization reference, and the reliable operation of the system is difficult to ensure, and meanwhile, the problems of communication delay, pulse interference and the like exist, namely, once false triggering, burrs or transient noise occur, the slave synchronization error is caused, and the control precision of the whole system is affected. Therefore, the existing one-master-multiple-slave carrier synchronization method has strong dependence, poor anti-interference performance and limited expandability, and cannot meet the requirements of high-precision and multi-node cooperative operation. Disclosure of Invention The invention aims to solve the problems of the prior art, and provides a carrier synchronization method and a synchronization control device based on an FPGA, which are used for solving the technical problems of low synchronization precision, poor stability and insufficient adaptability of the existing carrier synchronization method. By combining EtherCAT distributed clock technology and FPGA nanosecond timing control capability, high-precision synchronous carrier wave is generated, and the requirements of fields such as multi-axis synchronous control, distributed parallel inversion and the like on high precision and stability of multi-node cooperative operation are met. The above purpose is realized by the following technical scheme: a carrier synchronization method and a synchronization control device based on FPGA comprise the following steps: in the phase preprocessing stage, FPGA continuously captures the trigger signal of the global synchronous signal Sync0 generated by EtherCAT distributed clock mechanism, starts phase preprocessing when the Sync0 is triggered for the first time, judges whether the current Sync0 trigger time t 0 is in the effective adjustment interval of the carrier period, if yes, enters the step (2), if not, carries out preprocessing calibration operation; a phase verification stage, namely continuously capturing the next ten Sync0 trigger signals, judging each Sync0 trigger time one by one, verifying whether the Sync0 trigger time is in the effective adjustment interval, entering the step (3) if all the Sync0 trigger time is met, and returning to the step (1) if any trigger time is not met; And (3) in the dynamic synchronization adjustment stage, the Sync0 is used as a synchronization reference, the phase synchronization operation and the frequency error compensation operation are periodically executed on the carrier, and the EtherCAT distributed clock enables the synchronization precision of Sync0 signals generated by each node to be up to 20ns through detecting and calibrating the deviation of the local clock of each node and the bus reference clock in real time. Further, the preprocessing calibration operation specifically includes calculating a difference value DeltaX between a Count value of a carrier counter Count0 corresponding to a first Sync0 arrival time and a lower limit value F/F f–f·Ts of an adjustment effective interval, wherein F is a clock frequency of an FPGA synchronization module, F f is a carrier frequency, T s is a phase fixed delay, uniformly adjusting DeltaX per =DeltaX/64 to be within 64 subsequent carriers, and if a fraction exists in DeltaX per, adding one in an integer manner until T 0 falls into the adjustment effective interval. Further, the time range of the adjustment effective interval is [1/F f –Ts ,1/Ff ], and the corresponding carrier counter Count0 adjustment effective interval is [ F/F f–f·Ts ,f/Ff ],