CN-121984895-A - Method, device, system, electronic equipment and storage medium for extracting routing path of network-on-chip

CN121984895ACN 121984895 ACN121984895 ACN 121984895ACN-121984895-A

Abstract

The disclosure provides a method, a device, a system, electronic equipment and a storage medium for extracting a routing path of a network on chip, and relates to the technical field of electronic information. The network-on-chip comprises a plurality of router nodes and a plurality of on-chip processing units, wherein each router node is connected with at least one on-chip processing unit, the method comprises the steps of monitoring a path state indicating signal of each router node when a first on-chip processing unit of the network-on-chip accesses a second on-chip processing unit, and determining a routing path from the first on-chip processing unit to the second on-chip processing unit according to the signal state of the path state indicating signal of each router node. The scheme can improve the extraction efficiency of the routing path of the network-on-chip.

Inventors

Request for anonymity

Assignees

摩尔线程智能科技(北京)股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251223

Claims (12)

1. A method for extracting a routing path of a network-on-chip, wherein the network-on-chip comprises a plurality of router nodes and a plurality of processing units on-chip, and each router node is connected with at least one processing unit on-chip, the method comprises: Monitoring a path state indication signal of each router node when a first on-chip processing unit of the network on chip accesses a second on-chip processing unit; and determining a routing path from the first on-chip processing unit to the second on-chip processing unit according to the signal state of the path state indicating signal of each router node.
2. The routing path extraction method of a network on chip according to claim 1, wherein the router node is provided with a probe unit for monitoring a path state indication signal change of the router node, and the determining a routing path from the first on-chip processing unit to the second on-chip processing unit according to a signal state of the path state indication signal of each router node comprises: If the probe unit monitors that the path state indication signal of the router node changes, the router node is recorded as an intermediate router node; A routing path is determined from the first on-chip processing unit to the second on-chip processing unit based on each of the intermediate router nodes.
3. The routing path extraction method of a network on chip of claim 2, wherein said determining a routing path from the first on-chip processing unit to the second on-chip processing unit from each of the intermediate router nodes comprises: according to the time when the path state indication signal of each intermediate router node changes; Sequencing the intermediate router nodes according to the time sequence of the moments; And obtaining a routing path from the first on-chip processing unit to the second on-chip processing unit according to the sequencing result of the intermediate router nodes.
4. The method of routing path extraction for a network on chip of claim 2, further comprising: And extracting a path state indicating signal of the connected router node from each probe unit in a mode of back gate access.
5. The method of routing path extraction for a network on chip of claim 1, further comprising: determining one or more on-chip processing unit combinations, each of the on-chip processing unit combinations comprising a first on-chip processing unit and a second on-chip processing unit; the step of monitoring path status indication signals of the router nodes when a first on-chip processing unit of the network on chip accesses a second on-chip processing unit is performed for each of the on-chip processing unit combinations.
6. The method of claim 5, wherein the step of monitoring path status indication signals of each router node when a first on-chip processing unit of the on-chip network accesses a second on-chip processing unit is performed for each of the on-chip processing unit combinations, further comprising: And the step of monitoring the path state indication signals of the router nodes when the first on-chip processing unit of the on-chip network accesses the second on-chip processing unit is executed in parallel by combining the distributed independent threads through the on-chip processing units.
7. The method of routing path extraction for a network on chip of claim 1, further comprising: when the router node and the connected on-chip processing unit are added or subtracted from the on-chip network, a changed on-chip network is obtained; And returning to the step of monitoring the path state indication signals of the router nodes when the first on-chip processing unit of the on-chip network accesses the second on-chip processing unit based on the changed on-chip network.
8. The method of routing path extraction for a network on chip of claim 7, further comprising: setting a probe unit for the router node in the changed network-on-chip again; And generating a routing path according to the router node with the changed path state indication signal in the changed network-on-chip monitored by the probe unit.
9. The routing path extraction system of the network on chip is characterized by comprising the network on chip to be tested and electronic equipment, wherein: the network-on-chip to be tested comprises a plurality of router nodes and a plurality of on-chip processing units, and each router node is connected with at least one on-chip processing unit; The electronic device is communicatively coupled to the network-on-chip to be tested and configured to monitor path status indication signals of each router node when a first on-chip processing unit of the network-on-chip accesses a second on-chip processing unit, and to determine a routing path from the first on-chip processing unit to the second on-chip processing unit based on signal status of the path status indication signals of each router node.
10. A routing path extraction apparatus of a network on chip, wherein the network on chip includes a plurality of router nodes and a plurality of processing units on chip, and each router node is connected to at least one processing unit on chip, the apparatus comprising: A monitoring module, configured to monitor a path status indication signal of each router node when a first on-chip processing unit of the on-chip network accesses a second on-chip processing unit; And the routing path generation module is used for determining a routing path from the first on-chip processing unit to the second on-chip processing unit according to the signal state of the path state indication signal of each router node.
11. An electronic device, comprising: processor, and A memory having stored thereon computer readable instructions which, when executed by the processor, implement the routing path extraction method of a network on chip as claimed in any one of claims 1 to 8.
12. A computer readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the routing path extraction method of a network on chip according to any of claims 1 to 8.

Description

Method, device, system, electronic equipment and storage medium for extracting routing path of network-on-chip Technical Field The disclosure relates to the technical field of electronic information, in particular to a method, a device, a system, electronic equipment and a storage medium for extracting a routing path of a network on chip. Background Network-on-Chip (NoC) is a key technology for solving the problem of communication between multiple IP cores (processing units) in a large System-on-Chip (SoC), and provides excellent bandwidth performance, scalability, and reliability through Network interconnection called NoC links. The traditional NoC architecture consists of router nodes (R), IP cores, resource network interfaces, and tunnels. In such an architecture, the communication paths between different IP cores may be diverse. For example, when one IP core needs to communicate with another IP core, a series of different router nodes may be traversed to complete the data transfer. At present, in the traditional routing path extraction method of the network on chip, the whole chip is generally regarded as a black box, an IP core initiating a request is made to attempt to access a target IP core in a waveform simulation mode, and after the simulation is completed, the router nodes which specifically pass through are tracked by manually analyzing waveforms so as to extract a routing path. However, as the NoC scale is enlarged, the number of IP cores and the number of router nodes are increased, and the combination of routing paths becomes extremely complex, so that the conventional method for extracting routing paths of the network on chip consumes long time in the simulation process and the process of manually analyzing waveforms, and has the problem of low routing path extraction efficiency. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention An object of an embodiment of the present disclosure is to provide a method, an apparatus, a system, an electronic device, and a computer readable storage medium for extracting a routing path of a network on chip, which can improve the extraction efficiency of the routing path of the network on chip. Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure. According to a first aspect of an embodiment of the present disclosure, there is provided a routing path extraction method of a network on chip, the network on chip including a plurality of router nodes and a plurality of on-chip processing units, each of the router nodes being connected to at least one of the on-chip processing units, the method including: Monitoring a path state indication signal of each router node when a first on-chip processing unit of the network on chip accesses a second on-chip processing unit; and determining a routing path from the first on-chip processing unit to the second on-chip processing unit according to the signal state of the path state indicating signal of each router node. In some example embodiments of the present disclosure, based on the foregoing solution, the router node is provided with a probe unit, the probe unit is configured to monitor a change of a path status indication signal of the router node, and determine a routing path from the first on-chip processing unit to the second on-chip processing unit according to a signal status of the path status indication signal of each router node, including: If the probe unit monitors that the path state indication signal of the router node changes, the router node is recorded as an intermediate router node; A routing path is determined from the first on-chip processing unit to the second on-chip processing unit based on each of the intermediate router nodes. In some example embodiments of the present disclosure, based on the foregoing, the determining, according to each of the intermediate router nodes, a routing path from the first on-chip processing unit to the second on-chip processing unit includes: according to the time when the path state indication signal of each intermediate router node changes; Sequencing the intermediate router nodes according to the time sequence of the moments; And obtaining a routing path from the first on-chip processing unit to the second on-chip processing unit according to the sequencing result of the intermediate router nodes. In some example embodiments of the disclosure, based on the foregoing scheme, the method further comprises: And extracting a path state indicating signal of the connected router node from each probe unit in a mode of back gate access. In some example embodiments of the disclosure, based on the foregoing scheme,