CN-121985024-A - Binary data conversion and verification system for rail transit interlocking control system

CN121985024ACN 121985024 ACN121985024 ACN 121985024ACN-121985024-A

Abstract

The invention discloses a binary data conversion and verification system for a track traffic interlocking control system, which relates to the technical field of track traffic interlocking control systems and comprises a configuration analysis layer, a hardware interface layer, a sector allocation layer, a data structure mapping layer, a differential security protocol processing layer, a dual CRC32 check layer, a multi-stage data verification layer and a unified control interface layer. The invention comprehensively surpasses the prior art in the aspects of processing efficiency, accuracy, safety, resource utilization rate and the like through the key technical innovation of CELL abstract hardware interface design, differential security protocol processing, intelligent sector allocation algorithm and the like. The invention can effectively solve the key technical problem in the configuration management of the track traffic safety control system, provides a specialized configuration conversion solution for the VCU hardware platform, remarkably improves the system deployment and maintenance efficiency, and ensures the safe and reliable operation of the track traffic system.

Inventors

LIU HAOYANG
LIU LANG
WANG YIJIA
LIU JINGZE
FU LIYU
TANG WUMEI

Assignees

卡斯柯信号(成都)有限公司

Dates

Publication Date: 20260505
Application Date: 20260109

Claims (10)

1. Binary data conversion and verification system facing track traffic interlocking control system, which is characterized by comprising: the configuration analysis layer is used for reading and analyzing the JSON configuration file and generating a board card configuration set; the hardware interface layer is used for carrying out board card type identification and configuration normalization on the board card configuration set to generate standardized hardware configuration parameters; the sector allocation layer is used for allocating 64KB sector indexes to each board card according to the type of the board card and the physical slot position information, and generating a sector allocation scheme; The data structure mapping layer is used for mapping the standardized hardware configuration parameters into binary data structures conforming to VCU hardware specifications based on the sector allocation scheme, performing byte order processing and alignment filling, and generating a binary configuration file; The differentiated security protocol processing layer is used for filling security protocol fields into the communication board card and performing zero filling isolation on the non-communication board card, generating security protocol configuration data and writing the security protocol configuration data into a binary data structure; The dual CRC32 check layer is used for respectively calculating CRC32 for the global configuration header and the board card configuration data area, writing the CRC32 into the header, and outputting an integrity check result; The multi-stage data verification layer is used for carrying out multi-stage data verification on the binary configuration file and outputting a verification result; And the unified control interface layer is used for carrying out unified interface control and outputting a final binary configuration file and/or a verification result.
2. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein the hardware interface layer comprises: the CELL_COM communication unit is used for being responsible for network communication and comprises an IP address, port configuration, protocol type, security parameters and UNSAFETY multi-network type; The CELL_IM input module is used for processing input signals, and comprises channel configuration, input type, scanning period and BIT BIT mapping; The CELL_OM output module is used for controlling output signals, and comprises channel configuration, output type, update period, safety margin and BIT BIT mapping; And the CELL_FUNC functional unit is used for realizing special functions of system monitoring, data processing and logic control.
3. The system for converting and verifying binary data for an interlocking control system of track traffic according to claim 2, wherein the hardware interface layer is configured to abstract a physical board card type into a standardized CELL function combination, the physical board card type comprises an HCB communication board card, a SVCU control board card, a VOOB output board card and a VIIB mixed board card, wherein: HCB communication board = cell_com communication unit + cell_func functional unit, which is dedicated for secure communication; SVCU control board = cell_im input module + cell_om output module + cell_func functional unit, which is dedicated for IO control; in the hardware interface layer, a configuration mapping technology is adopted, wherein each board card internally comprises a plurality of CELL units of different types, a data stream and a control stream are defined through a mapping relation among CELL units, and the dynamic expansion of new CELL types is supported without modification.
4. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein the configuration parsing layer comprises: The configuration verifier is used for verifying the type legality of the necessary root field, the upper limit of the number of the boards and the key field of the JSON configuration file to generate a verification result; The board type identifier is connected with the configuration verifier, analyzes nodes of communication_rack and board_ configurations based on a verification result, identifies HCB communication board, SVCU control board and VOOB output board and VIIB mixed board types and generates board type information; The JSON analysis engine is used for analyzing the complex nested JSON configuration file, extracting basic parameters of the board card, analyzing session configuration of the communication board card and generating configuration data information; the CELL unit mapper is respectively connected with the board type identifier and the JSON analysis engine, performs field normalization, redundancy inheritance and parameter mapping based on the board type information and the configuration data information, and generates functional unit configuration, input module configuration, output module configuration, communication unit configuration and output board configuration set.
5. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein the sector allocation layer comprises: the third-level priority module is used for determining allocation priority according to the type of the board card and generating a priority result; The topology perception processor is connected with the three-level priority module, and performs topology sequencing on the same-priority board cards according to the rack ID, the slot position ID and the left and right positions based on the priority result to generate a topology sequencing result; The dynamic address distributor is connected with the topology perception processor, distributes 64KB sector indexes for each board card based on a topology sequencing result and generates an address distribution table; And the conflict detector is connected with the dynamic address distributor, detects sector conflicts and continuity based on an address distribution table and outputs a final sector distribution result.
6. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein the data structure mapping layer comprises: The global configuration header constructor generates LRU index entries based on the sector allocation result, counts the number of the boards and the global IO bits, and generates a global configuration header; the card board configuration generator is connected with the global configuration head constructor, constructs a card board configuration structure based on the global configuration head and the card board configuration set and generates card board configuration data; The CELL parameter filler is connected with the card board configuration generator, and fills session parameters, remote IP, security protocols and IO mapping parameters into corresponding structure fields based on card board configuration data to generate a card board configuration binary fragment; and the byte order processor is connected with the CELL parameter filler, and is used for executing byte order processing on the multi-byte field based on the board card configuration binary fragment, and performing 4-byte boundary alignment and 64KB sector filling to generate a binary configuration file.
7. The system for binary data conversion and verification for rail transit interlock control system according to claim 1, wherein the differential security protocol processing layer comprises: The CELL_IM/OM zero-filling module is used for performing zero-filling on the security protocol field of the non-communication board card to realize security isolation; the CELL_COM security filling module is used for extracting security_traffic parameters from session configuration for the communication board card, completing protocol type mapping and field analysis, filling security parameters into a security protocol descriptor array and generating security protocol parameters; the security isolation controller is used for ensuring that security protocol parameters are only written into the communication board card configuration area and the security field of the non-communication board card is kept at a zero value; and the RSSP1 protocol processor is connected with the CELL_COM security filling module, performs default processing and consistency check based on security protocol parameters, and outputs security protocol fields which can be used for structural body mapping.
8. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein the dual CRC32 check layer comprises: a header CRC calculator for calculating CRC32 for data of the global configuration header except the CRC field and writing HEADERCRC fields to generate a header check; The data CRC calculator is used for calculating CRC32 of the board configuration data area and writing dataCRC fields into the data area to generate data check; and the integrity verifier is respectively connected with the head CRC calculator and the data CRC calculator and is used for comparing the recalculated value with the written value and outputting error type and positioning information when the recalculated value and the written value are inconsistent, so as to generate an integrity result.
9. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein in the multi-level data verification layer, the multi-level data verification comprises: verifying an infrastructure, namely checking the validity of a file size, sector alignment and header fields; CRC32 integrity checking, namely a double checking mechanism verifies the integrity of data transmission; Verifying the type code of the board card, the uniqueness of the sector index and the configuration correctness of the security protocol; checking the hardware compatibility, namely checking a product identifier, reserving field zero filling and memory alignment requirements; In the multi-stage data verification layer, an error processing strategy is adopted, namely a hierarchical error report is generated, accurate error positioning is carried out, and an intelligent repair suggestion is generated.
10. The track traffic interlocking control system oriented binary data conversion and verification system according to claim 1, wherein the unified control interface layer comprises: the API interface is used for providing a unified call inlet for conversion, analysis and verification and generating an API call; The command line interface is connected with the API interface and outputs an execution state, error information and a visualized/batch processing command inlet based on an API call and a verification result; The visual display device is connected with the command line interface and is used for carrying out structural display on the analysis/verification result based on the visual demand command; and the batch processor is connected with the command line interface, and is used for executing batch analysis, batch verification or batch conversion on a plurality of input files based on the batch processing command and generating a summary report.

Description

Binary data conversion and verification system for rail transit interlocking control system Technical Field The invention relates to the technical field of rail transit interlocking control systems, in particular to a binary data conversion and verification system for a rail transit interlocking control system, and particularly relates to a binary configuration file automatic conversion system serving a VCU (vital control unit, software security platform). The specific technical field is subdivided as follows: 1. Main technical field The rail traffic signal control system comprises a CBTC, a CTCS and other modern train control systems; safety critical system configuration management, configuration data processing technology of SIL4 safety integrity level; Binary data conversion of the embedded system, namely a data format conversion technology special for a hardware platform. 2. Direct application scenario VCU200/VCU118 hardware platform, configuration data generation based on 64KB sector architecture; and the multi-board system configuration conversion supports 42 board card architectures such as HCB communication board cards, SVCU control board cards and the like. 3. Cross-technology field Real-time system configuration engineering, namely millisecond configuration conversion and deployment technology; The security protocol stack integration is supported by special protocols of rail transit such as USIG, RSSP1 and the like; Industrial automation configuration management, a configuration standardization technology of a large-scale industrial control system. Background In the rail transit interlocking control system, binary data conversion and verification are often required to ensure the running safety of the train. 1. Chinese patent application CN117104317A, station crossing interlocking general processing method In the prior art, the patent with the publication number of CN117104317A discloses a general processing method for interlocking of a crossing in a station, and the patent adopts a layered interlocking logic processing architecture and realizes general processing through a standardized crossing control template library. As shown in fig. 3, the technical architecture includes a template definition layer (predefining a standard crossing control template), a parameter mapping layer (establishing a mapping relation between the template and engineering parameters), a logic generation layer (generating XML format interlocking logic based on a rule matching engine), and a verification deployment layer (ensuring logic security through Petri net verification and simulation test). The method comprises the processing flows of engineering demand analysis, template library retrieval matching, parameter form filling, XML logic generation, simulation verification and field deployment. The technical proposal of the patent has low resource utilization rate. Since the template library needs to cover all possible crossing scene combinations, the number of templates required will reach thousands when faced with a 42 board by multiple configuration parameter combination of the VCU200 system. Each template occupies about 50-100KB of memory, the total memory requirement exceeds 500MB, while VCU200 hardware memory is only 256MB, and resource utilization exceeds hardware bearing capacity. The technical root of the excessive calculation load is that the time complexity of the template matching algorithm is O (m multiplied by n), wherein m is the number of templates, and n is the feature vector dimension. When dealing with complex configurations of 42 boards, feature vector dimensions reach hundreds, and the computational load grows quadratically, resulting in configuration generation times extending from the minute level to the hour level. 2. Configuration management technical scheme based on CBTC system The CBTC configuration management system adopts a classical four-layer architecture mode, as shown in figure 4, a data persistence layer stores basic configuration information such as track geometry, signal equipment and the like by using an Oracle/PostgreSQL database, a service logic layer realizes configuration version control and change approval based on a J2EE/Spring framework, a data transmission layer adopts a TCP/IP protocol stack to combine with a private application layer protocol to realize network distribution, and a device access layer deploys a configuration agent program to be responsible for local analysis and application. The technical process comprises configuration editing, format verification, version storage, approval process, distribution synchronization, local analysis and equipment application, wherein an IEEE 1474.1 standard XML_Schema description configuration data structure is adopted, and the efficiency and the integrity of data transmission are ensured through an incremental updating mechanism and an MD5 check code. The configuration management technical scheme based on the CBTC system has the t