CN-121985039-A - Extensible high concurrency data cache management system

CN121985039ACN 121985039 ACN121985039 ACN 121985039ACN-121985039-A

Abstract

The expandable high concurrency data buffer memory management system solves the problem of how to realize expandable, high concurrency and non-blocking buffer memory, and belongs to the crossing field of integrated circuit design and computer network communication technology. The invention comprises a plurality of input port service subsystems and a plurality of output port service subsystems which are independently parallel, and realize the configurable expansion of the quantity of the input port service subsystems and the output port service subsystems through independent chip selection signal control and enable, wherein the input port service subsystems are used for receiving data streams from physical ports for preprocessing and protocol analysis, the scheduling subsystem is used for carrying out scheduling decision and virtual output queue management of data packets to realize multi-level QoS scheduling, the buffer subsystem is used for storing, address allocation, multicast support and memory recovery of the data packets, and the output port service subsystem is used for reading data from the buffer and sending the data to the physical ports. The present invention also supports error checking and correction mechanisms.

Inventors

HUO MINGXUE
ZHOU HONGYI
QI CHUNHUA
YANG YUTAO
ZHANG JINLEI

Assignees

哈尔滨工业大学

Dates

Publication Date: 20260505
Application Date: 20260130

Claims (10)

1. The scalable high concurrency data cache management system is characterized by comprising a scheduling subsystem, a cache subsystem, a plurality of input port service subsystems and a plurality of output port service subsystems; the plurality of input port service subsystems and the plurality of output port service subsystems are independently parallel, and the number of the input port service subsystems and the number of the output port service subsystems can be expanded in a configurable way through controlling and enabling the independent chip selection signals; Each input port service subsystem is connected with the scheduling subsystem and the cache subsystem at the same time and is used for receiving and preprocessing data streams from corresponding physical ports, sending a data packet writing request to the scheduling subsystem according to the parsed data packets, writing the corresponding data packets into the cache subsystem according to a writing authorization signal fed back by the scheduling subsystem, and sending control information of the data packets to the scheduling subsystem; The scheduling subsystem is connected with the cache subsystem and the output port service subsystem at the same time, and is used for feeding back a write-in authorization signal to the corresponding input port service subsystem according to the storage resource state of the cache subsystem when receiving a data packet write-in request, receiving the control information from each input port, and performing virtual output queue management on the SRAM address of the data packet in the cache subsystem, wherein the virtual output queue is logically isolated according to the destination port and the priority of the data packet so as to realize non-blocking access; The cache subsystem is connected with all the output port service subsystems at the same time and is used for storing the data packets from the input port service subsystem, executing address allocation, responding to the read request and the SRAM address of the scheduling subsystem, reading the corresponding data packets and outputting the data packets to the output port service subsystem through the scheduling subsystem; And each output port service subsystem is used for carrying out post-processing on the data packet read from the cache subsystem and outputting the data packet.
2. The scalable high concurrency data buffer management system of claim 1, wherein the scheduling subsystem comprises a write arbitration module, a sort summary and VOQ management module, a codec QoS scheduling module, and an output transit module; The write arbitration module is connected with each input port service subsystem, the cache subsystem and the classified summary and VOQ management module at the same time, and is used for receiving a data packet write request sent by the input port service subsystem, arbitrating according to the storage resource state of the cache subsystem, feeding back a write authorization signal to the input port service subsystem after confirming that the corresponding SRAM can receive the data packet, and simultaneously splicing the storage address, byte number and source port information of the corresponding data packet into an address byte signal, and sending the address byte signal, the destination port signal and the priority signal to the classified summary and VOQ management module; the classifying, summarizing and VOQ management module is connected with the encoding and decoding QoS scheduling module and is used for storing SRAM addresses of the data packets into corresponding virtual output queues according to the received destination port signals and priority signals, and each virtual output queue corresponds to different destination ports and priorities; The encoding and decoding QoS scheduling module is connected with the output transfer module and is used for scanning a plurality of corresponding priority virtual output queues according to a set service quality scheduling strategy aiming at each output port, selecting the SRAM address of a data packet to be read and sending the selected SRAM address to the output transfer module; And the output transfer module is connected with the cache subsystem and the output port service subsystem at the same time and is used for receiving the SRAM address sent by the encoding and decoding QoS scheduling module, sending a read request to the cache subsystem according to the source port information in the SRAM address, and connecting the read data returned by the cache subsystem to the corresponding output port service subsystem so as to finish the reading and forwarding of the data packet.
3. The scalable high concurrency data cache management system of claim 2, wherein the quality of service scheduling policy is strict priority mode: And for any output port service subsystem, always preferentially scheduling SRAM addresses in the highest priority virtual output queue, and sequentially scheduling the next priority virtual output queue only when the highest priority queue is empty.
4. The scalable high concurrency data cache management system of claim 2, wherein the quality of service scheduling policy is a weighted poll mode: and aiming at any output port service subsystem, polling and scheduling SRAM addresses in each priority virtual output queue according to the weight proportion preset for each priority queue so as to prevent data packets of low-priority queues from being not scheduled for a long time.
5. The scalable high concurrency data cache management system of claim 1, wherein the input port service subsystem comprises a FIFO write module, a data parsing unit, an ECC check coding unit, and a read enable control unit; The FIFO writing module is connected with the data analysis unit and is used for adopting an asynchronous FIFO as a cross-clock domain buffer area, receiving the data stream from the corresponding physical port and outputting the buffered data stream to the data analysis unit; The data analysis unit is connected with the ECC check coding unit and the scheduling subsystem at the same time and is used for analyzing the input data stream, extracting the control information of the data packet, separating out the effective load data, sending the control information to the scheduling subsystem and sending the effective load data to the ECC check coding unit; the ECC check coding unit is connected with the read enabling control unit and is used for performing error checking and correction coding on the payload data, generating a write-in data stream and sending the write-in data stream to the read enabling control unit; The read enabling control unit is connected with the cache subsystem and the scheduling subsystem at the same time and is used for receiving the write-in data stream from the ECC check coding unit and controlling the write-in data stream to be written into the cache subsystem according to a write-in authorization signal fed back by the scheduling subsystem.
6. The scalable high concurrency data cache management system of claim 5, wherein the data parsing unit is configured to parse the incoming data stream using a finite state machine.
7. The scalable high concurrency data cache management system of claim 5, wherein the control information includes destination port number, priority, multicast labels, and data length.
8. The scalable high concurrency data buffer management system of claim 5, wherein the ECC check coding unit is configured to perform error checking and correction coding on the 32-bit payload data, generate 7-bit check bits, splice the 7-bit check bits to the 32-bit payload data, and send the 7-bit check bits as a write data stream to the read enable control unit.
9. The scalable high concurrency data cache management system of claim 1, wherein the cache subsystem comprises a hybrid storage pool management module, an intelligent multicast support module, and an address allocation and memory reclamation module; The system comprises a mixed storage pool management module, an intelligent multicast support module, a reference count value and a reference count update state, wherein the mixed storage pool management module is connected with each input port service subsystem, a scheduling subsystem and the intelligent multicast support module at the same time, is used for managing storage resources consisting of a special cache and a shared cache, distributing write requests from different input port service subsystems and read requests from the scheduling subsystem to corresponding physical RAM blocks through a multi-path mapping table so as to support concurrent access of multiple ports and complete corresponding write and read operations, and is also used for receiving an initial reference count value issued by the intelligent multicast support module and binding with a storage address when writing and reading multicast data packets; The intelligent multicast support module is connected with the address allocation and memory recovery module and is used for managing multicast data packets by adopting a reference counting mechanism, setting initial reference counts according to the number of destination ports when the multicast data packets are written in and issuing the initial reference counts to the mixed memory pool management module; The address allocation and memory reclamation module is connected with the mixed memory pool management module and is used for dynamically allocating memory addresses for written data packets, receiving a physical RAM block release notification from the mixed memory pool management module and reclaiming the addresses to realize dynamic multiplexing.
10. The scalable high concurrency data buffer management system of claim 1, wherein the output port service subsystem FIFO buffer module, ECC decoding verification unit, and data reassembly and packaging module; The FIFO reading module is connected with the cache subsystem and the ECC decoding and checking unit at the same time, and is used for buffering the data stream read from the cache subsystem by adopting an asynchronous FIFO and outputting the data stream to the ECC decoding and checking unit; The ECC decoding and checking unit is connected with the data reorganizing and packaging module and used for carrying out error checking, correcting and decoding on the buffered data stream and sending corrected effective load data to the data reorganizing and packaging module; And the data reorganization and packaging module is used for reorganizing the corrected effective load data into complete data packets according to the length information of the data packets, and outputting the complete data packets after adding control information.

Description

Extensible high concurrency data cache management system Technical Field The invention relates to an extensible high concurrency data cache management system, belonging to the crossing field of integrated circuit design and computer network communication technology. Background With the rapid development of cloud computing, large data centers and artificial intelligence cluster computing, the flow characteristics of data center networks have changed deeply. The explosive growth of East-west traffic (East-WEST TRAFFIC), and the Micro-bursts generated by distributed computing applications, presents unprecedented challenges to the port rate and cache management capabilities of network switching devices. In a high performance network switching architecture, packet Buffer (Packet Buffer) management is one of the key factors that determine the performance of a switch. The primary responsibility of the buffer management module is to buffer packets between the input and output ports to absorb traffic bursts, resolve port congestion, and support quality of service (QoS) scheduling. The design of the cache architecture directly affects the Throughput (Throughput), the Latency (Latency) from end to end (Packet Loss Rate) of the switch. The current data caching architecture is mainly divided into three main forms of Input Queuing (IQ), output Queuing (OQ) and Shared Memory (SM), and each of them has a physical or logical bottleneck that is difficult to overcome. Input Queuing (IQ) and head of line blocking (HOL) problems in input queuing architectures, packets are stored in the input port's cache. This architecture requires less bandwidth on the memory and only requires equal port rates. However, it has a well-known Head-of-Line (HOL) problem. When a message at the head of the queue cannot be sent due to congestion of the target output port, messages destined for other non-congested ports that are queued behind it are blocked. Theoretical studies have shown that HOL blocking will result in a maximum throughput limit of the switch around 58.6% at uniform traffic. Output Queuing (OQ) and memory wall problems-output queuing architecture places a cache at an output port. This architecture provides the best delay and throughput performance because packets are switched to the output port immediately after arrival. However, this requires that the write rate of the switch fabric and output buffer must be the sum of all input port rates, i.e., have a N-fold speed ratio (Speedup). In a multiport high speed switch, this can result in memory bandwidth requirements far exceeding the read-write limits of physical SRAM or DRAM. For example, a 16-port 10G switch, if using pure output queuing, has a central memory bandwidth of 320Gbps or more, and needs to support very high frequency concurrent read/write, which is very challenging and power consuming for engineering implementation. Shared caching (SM) and management complexity-shared caching architecture is considered to be the best solution to balance performance and resource utilization. All input and output ports share a global memory pool. Compared with static division, the shared buffer can better utilize limited on-chip storage resources, and the burst traffic of each port is absorbed through the statistical multiplexing principle. However, designing an efficient shared cache management module faces three types of problems, namely, blocking and performance bottleneck during ① multi-port concurrent access, storage resource waste and inefficiency caused by ② fixed partition, and coarse granularity of ③ quality of service (QoS) scheduling. Disclosure of Invention Aiming at the problem of how to realize extensible, high concurrency and non-blocking caching, the invention provides an extensible and high concurrency data cache management system. The invention relates to an extensible high concurrency data cache management system, which comprises a scheduling subsystem, a cache subsystem, a plurality of input port service subsystems and a plurality of output port service subsystems, wherein the scheduling subsystem is used for scheduling data; the plurality of input port service subsystems and the plurality of output port service subsystems are independently parallel, and the number of the input port service subsystems and the number of the output port service subsystems can be expanded in a configurable way through controlling and enabling the independent chip selection signals; Each input port service subsystem is connected with the scheduling subsystem and the cache subsystem at the same time and is used for receiving and preprocessing data streams from corresponding physical ports, sending a data packet writing request to the scheduling subsystem according to the parsed data packets, writing the corresponding data packets into the cache subsystem according to a writing authorization signal fed back by the scheduling subsystem, and sending control information of the data packets to t