CN-121985146-A - Multi-bus decoupling distributed embedded hardware rendering architecture, system and method

CN121985146ACN 121985146 ACN121985146 ACN 121985146ACN-121985146-A

Abstract

The invention discloses a multi-bus decoupling distributed embedded hardware rendering architecture, a system and a method, which relate to the technical field of ultra-high definition video hardware processing and have the technical scheme that the multi-bus decoupling distributed embedded hardware rendering architecture comprises a multi-bus decoupling module, a multi-bus processing module and a multi-bus processing module, wherein the multi-bus decoupling module comprises a plurality of mutually physically isolated hardware buses, and each hardware bus is a dedicated hardware transmission link for bearing a single type of manufacturing task; the modularized processing units are independent hardware boards and are integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port, the modularized processing units are sequentially cascaded through hardware buses in the multi-bus decoupling module to form a distributed pipeline rendering link, and when the modularized processing units are newly added, the signal processing capacity and the rendering synthesis capacity are linearly improved along with the increase of the number of the modularized processing units. The invention fundamentally solves the performance bottleneck problem of the traditional architecture when processing 4K/8K ultrahigh definition and multi-channel rendering.

Inventors

WANG WEI
LUO TIAN
WEN XUMING
SHE JUN

Assignees

成都索贝数码科技股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260408

Claims (10)

1. A multi-bus decoupled distributed embedded hardware rendering architecture, comprising: the multi-bus decoupling module comprises a plurality of mutually physically isolated hardware buses, wherein each hardware bus is a dedicated hardware transmission link for bearing a single type of manufacturing task; The system comprises a plurality of modularized processing units with different functions, wherein each modularized processing unit is an independent hardware board card and is integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port; When the modularized processing units are newly added, the signal processing capacity and the rendering synthesis capacity of the whole system are linearly improved along with the increase of the number of the modularized processing units.
2. The distributed embedded hardware rendering architecture of claim 1, wherein a plurality of the hardware buses are independently wired in hardware, and no data interaction exists between the plurality of the hardware buses; And each hardware bus integrates a hardware synchronization calibration unit, and hardware logic is aligned with a frame header through homologous clock distribution to realize multi-bus signal synchronization.
3. The multi-bus decoupled distributed embedded hardware rendering architecture of claim 1, wherein the plurality of functionally differentiated modular processing units comprises at least two of a base input processing unit, a base rendering processing unit, and a core specialized rendering processing unit; The basic input processing unit is used for converting the received external multi-source heterogeneous signals into baseband signals unified in the framework; The base rendering processing unit is used for executing base rendering processing on the received baseband signal; The core professional rendering processing unit is used for executing high-order professional rendering processing on the received baseband signal or file stream.
4. A multi-bus decoupled distributed embedded hardware rendering architecture according to claim 3, wherein the base input processing unit hardware is integrated with at least one of SDI, ST2110, NVI, NDI and SRT signal input interfaces; The basic rendering processing unit is integrated with at least one of SDI, NVI, NDI and SRT signal input interfaces by hardware, and is provided with a basic rendering hardware module for realizing color space conversion, switching, digital video special effects, mixing, cutting or multi-picture superposition; the core professional rendering processing unit is integrated with at least one of SDI and video and audio file input interfaces by hardware, and is provided with professional rendering hardware modules for realizing signal switching, keying, downstream key, digital video special effects, mixing, cutting or multi-picture superposition.
5. The architecture of claim 1, wherein the hardware circuits and functional modules of the modular processing unit are designed differently according to their processing functions.
6. The distributed embedded hardware rendering architecture of claim 1, wherein the architecture supports a single signal input through the modular processing unit, distributing processed signals to downstream multiple corresponding ones of the hardware buses for parallel processing.
7. The multi-bus decoupled distributed embedded hardware rendering architecture of any of claims 1-6, wherein the plurality of hardware buses includes a main playout PGM bus, a pre-monitor PVW bus, and a multi-picture monitor MV bus.
8. A slow motion and highlight playback system employing a multi-bus decoupled distributed embedded hardware rendering architecture as claimed in any one of claims 1-7, comprising: The external signal input port of the at least one basic rendering processing unit is used for accessing external camera signals, and the upstream bus signal input port and the downstream bus signal output port of the at least one basic rendering processing unit are respectively connected to an MV bus and used for realizing signal recording and MV bus multi-picture basic rendering; the at least one first core professional rendering processing unit accesses file storage through a tera-meganet interface, and an upstream bus signal input port of the at least one first core professional rendering processing unit is connected to the PGM bus and the MV bus and is used for realizing video file decoding, variable speed processing and multi-picture superposition rendering; The at least one second core professional rendering processing unit accesses the file storage through a tera-meganet interface, an upstream bus signal input port is connected to the PGM bus and the MV bus, and a downstream bus signal output port is connected to a PGM broadcasting output interface and an MV monitoring output interface, and is used for realizing file multi-picture decoding, multi-picture fusion rendering with MV bus signals and final signal output.
9. An oversized multi-picture stitching system, characterized in that a multi-bus decoupled distributed embedded hardware rendering architecture according to any of claims 1-7 is applied, comprising: A plurality of basic input processing units for accessing the ST2110 signals; The base rendering processing unit is used for accessing the SDI, the NVI and the network stream signals and performing picture splicing processing; At least one core professional rendering processing unit for accessing the file and performing multi-path multi-picture bus splicing and picture splicing output processing; the number of hardware buses in the multi-bus decoupling module is four.
10. A method for rendering multi-bus decoupled distributed embedded hardware, applied to a multi-bus decoupled distributed embedded hardware rendering architecture as claimed in any one of claims 1-7, the method comprising: Transmitting signals through a plurality of hardware buses physically isolated from each other, wherein each hardware bus is dedicated to carrying a single type of manufacturing task; Carrying out distributed pipeline processing on signals through a plurality of modularized processing units with different functions, wherein each modularized processing unit is an independent hardware board card capable of being freely combined and cascaded; When the modularized processing unit is newly added, the modularized processing unit is cascaded into a link formed by a plurality of hardware buses, so that the signal processing and rendering synthesis capacity of the whole system is linearly improved.

Description

Multi-bus decoupling distributed embedded hardware rendering architecture, system and method Technical Field The invention relates to the technical field of ultra-high definition video hardware processing, in particular to a multi-bus decoupling distributed embedded hardware rendering architecture, a system and a method. Background The ultra-high definition (4K/8K) technology is rapidly popularized in the large audiovisual industry, and key application scenes such as live broadcasting of sports events, large-scale artistic evening, medium-fusion studio, large screen of command center and the like are widely adopted in a multi-source heterogeneous signal hybrid access mode such as SDI, ST2110 and NVI, so that extremely high requirements are provided for performance, expandability and reliability of a hardware rendering architecture. Currently, the industry mainstream adopts a centralized embedded hardware rendering architecture, which relies on a single chip or a single board card to complete the full flow processing of signals. The existing few improved schemes only perform local optimization aiming at single bus bandwidth or general module splitting, and cannot fundamentally solve the core problem of a hardware architecture. The system mainly comprises a centralized architecture, wherein the processing capability of a single chip or a single board card has an inherent upper limit, multi-channel parallel rendering of ultra-high definition signals is difficult to support, computational power is insufficient and the requirement of multi-task parallel processing cannot be met, the system is high in expansion cost and prolonged in deployment period due to lack of modularized stacking capability when signal input paths are newly added or channels are manufactured, dynamic changes of services cannot be adapted due to the fact that hardware equipment is required to be integrally replaced, the existing bus design adopts a single-bus multi-task sharing mode, a single-bus multi-task sharing mode is adopted for broadcasting, pre-monitoring and monitoring task competition bus resources, a physical isolation mechanism is omitted, single-point faults possibly cause whole system paralysis, reliability is low, the existing hardware modules are split only based on general functions, differential designs aiming at large audio-visual industries are lacked, no perception cascade can not be realized among the modules, system performance cannot be linearly improved when the modules are newly added, and the utilization rate of hardware resources is low. The above-mentioned drawbacks of the hardware architecture level make it difficult for the conventional scheme to adapt to the hardware requirements of the new generation of ultra-high definition video production. Accordingly, there is a pressing need in the industry for a distributed embedded hardware rendering architecture that enables performance stacking, has high reliability, and supports flexible extensions. Disclosure of Invention In order to solve the defects in the prior art, the invention aims to provide a multi-bus decoupling distributed embedded hardware rendering architecture, a system and a method, and by adopting the design of flexible cascading of physical isolation and modularized processing units of a multi-bus decoupling module, a centralized processing mode relying on a single chip or a single board card is abandoned in principle, the overall processing task is decomposed into a plurality of independent modularized processing units to be executed in parallel, and the overall computing capacity of the system can be directly improved by adding the modularized processing units. The technical aim of the invention is realized by the following technical scheme: In a first aspect, a distributed embedded hardware rendering architecture for multi-bus decoupling is provided, comprising: the multi-bus decoupling module comprises a plurality of mutually physically isolated hardware buses, wherein each hardware bus is a dedicated hardware transmission link for bearing a single type of manufacturing task; The system comprises a plurality of modularized processing units with different functions, wherein each modularized processing unit is an independent hardware board card and is integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port; When the modularized processing units are newly added, the signal processing capacity and the rendering synthesis capacity of the whole system are linearly improved along with the increase of the number of the modularized processing units. Furthermore, the plurality of hardware buses adopt independent wiring design on hardware, and no data interaction exists among the plurality of hardware buses; And each hardware bus integrates a hardware synchronization calibration unit, and hardware logic is aligned with a frame header through homologous clock distribution to realize multi-bus