CN-121985231-A - Pixel front-end circuit, pixel sensor and detector system

CN121985231ACN 121985231 ACN121985231 ACN 121985231ACN-121985231-A

Abstract

The application discloses a pixel front-end circuit, a pixel sensor and a detector system, and relates to the technical field of power electronics, wherein an input stage and a charge transfer amplifying branch circuit in the pixel front-end circuit comprise a source follower tube, a first common-source common-gate shielding tube, a load current source and a current feedback network; the current feedback network comprises a feedback capacitor, a first feedback transistor and a second feedback transistor, the bias and baseline setting network comprises a main bias current tube and a threshold current and baseline recovery circuit, the threshold current and baseline recovery circuit comprises the first feedback transistor and the second feedback transistor, and the judging output stage and the second cascode shielding module comprise a load tube, a second cascode shielding tube and an input tube. The pixel front-end circuit of the application meets the requirements of low power consumption, high uniformity and high detection performance in a limited area.

Inventors

XIAO LE
ZHANG GUOXIANG
ZHANG YU
ZHONG CHENG

Assignees

华中师范大学

Dates

Publication Date: 20260505
Application Date: 20260331

Claims (10)

1. The pixel front-end circuit is characterized by comprising an input stage, a charge transfer amplifying branch, a bias and baseline setting network and a judging output stage and a second cascode shielding module; The input stage and the charge transfer amplifying branch circuit comprise a source electrode follower tube, a first cascode shielding tube, a load current source and a current feedback network, wherein the current feedback network comprises a feedback capacitor, a first feedback transistor and a second feedback transistor; the bias and baseline setting network comprises a main bias current tube and a threshold current and baseline restoration circuit, wherein the threshold current and baseline restoration circuit comprises a first feedback transistor and a second feedback transistor; the judging output stage and the second cascode shielding module comprise a load tube, a second cascode shielding tube and an input tube.
2. The pixel front-end circuit of claim 1, wherein in the input stage and charge transfer amplification branch, a gate of the source follower transistor is connected to an input node, a source of the source follower transistor is connected to a charge transfer node, the input node is directly connected to an N-type collection well ohmic contact of a sensor to receive collected charges of the N-type collection well, a source of the first cascode shield transistor is connected to a drain of the source follower transistor, a drain of the first cascode shield transistor is connected to a first stage output node, a gate of the first cascode shield transistor is connected to a first PMOS bias voltage, a source of the load current source transistor is grounded, a drain of the load current source transistor is connected to a first stage output node, a gate of the load current source transistor is connected to a feedback node, one end of the feedback capacitor is connected to the charge transfer node, another end of the feedback capacitor, a drain of the first feedback transistor and a drain of the second feedback transistor are connected to a feedback node, a gate of the first feedback transistor is connected to a first PMOS bias voltage, and a drain of the first feedback transistor is connected to a first stage output voltage.
3. The pixel front-end circuit of claim 2, wherein in the bias and baseline setting network, a gate of the main bias current tube is connected to a third PMOS bias voltage, a source of the main bias current tube is connected to a supply voltage, and a drain of the main bias current tube is connected to a charge transfer node.
4. The pixel front-end circuit of claim 3, wherein in the discrimination output stage and the second cascode shielding module, a gate of the load tube is connected to a fourth PMOS bias voltage, a source of the load tube is connected to a power supply voltage, a drain of the load tube is connected to a second stage output node, a gate of the second cascode shielding tube is connected to a second NMOS bias voltage, a drain of the second cascode shielding tube is connected to a second stage output node, a source of the second cascode shielding tube is connected to a drain of the input tube, a source of the input tube is grounded, and a gate of the input tube is connected to the first stage output node.
5. The pixel front-end circuit of claim 4, further comprising a pulse clipping module; the pulse amplitude limiting module comprises an amplitude limiting transistor; and the grid electrode of the limiting transistor is connected with a fifth PMOS bias voltage, the source electrode of the limiting transistor is connected with a feedback node, and the drain electrode of the limiting transistor is connected with a first-stage output node.
6. The pixel front-end circuit of claim 5, wherein the source follower transistor, the first cascode shield transistor, the load current source, the main bias current tube, the first feedback transistor, the second feedback transistor, the load transistor, the second cascode shield transistor, the input transistor, and the clipping transistor are all metal-oxide semiconductor field effect transistors, each configured to operate in a weak inversion region.
7. The pixel front-end circuit of claim 5, wherein the source follower transistor, the load current source, the main bias current tube, the first feedback transistor, the second feedback transistor, the load transistor, the input transistor, and the clipping transistor are all metal-oxide semiconductor field effect transistors; the first cascode shield and the second cascode shield the source common grid shielding pipes are all gain bootstrap operational amplifiers.
8. The pixel front-end circuit of claim 1, wherein the feedback capacitance is a MIM capacitance.
9. A pixel sensor comprising an array of pixels, at least one pixel cell in the array of pixels comprising a pixel front-end circuit as claimed in any one of claims 1-8.
10. A detector system comprising a pixel sensor and a data acquisition circuit as claimed in claim 9; the data acquisition circuit is connected to the second-stage output node of the pixel front-end circuit in each pixel unit and is used for receiving pulse signals.

Description

Pixel front-end circuit, pixel sensor and detector system Technical Field The present application relates to the field of power electronics, and in particular, to a pixel front-end circuit, a pixel sensor, and a detector system. Background The pixel sensor is a core detection device of a new generation of high-energy physical experiment and high-end Complementary Metal Oxide Semiconductor (CMOS) image sensor, and a front-end circuit of the pixel sensor generally adopts a traditional architecture of a source follower and a discriminator. However, this architecture, when oriented towards larger scale, higher performance applications, presents the following fundamental contradictions that are difficult to overcome: First, there is a direct conflict between power consumption and speed/gain. To obtain high gain and fast response, the bias current needs to be increased, which leads to a sharp rise in the total power consumption of the pixels, and cannot meet the heat dissipation and power consumption limitations of large-scale arrays. Secondly, uniformity and integration are mutually restricted. To improve uniformity of threshold and response time, transistor area is increased to suppress mismatch, but this contradicts the stringent requirements of fine pixel pitch for circuit area. Moreover, the relative variation of parasitic capacitance under deep submicron process is remarkable, and the uniformity of gain and threshold value between pixels is directly affected, while the traditional circuit lacks effective inhibition means. In addition, the conventional architecture has insufficient large signal processing capability, and when the input charge is too large, the output pulse can be stretched in a nonlinear manner, which results in time information distortion, increased dead time and complexity of global timing design. Therefore, the conventional architecture is difficult to meet the requirements of low power consumption, high uniformity, strong anti-parasitic interference and wide dynamic range in a limited area, and has become a key bottleneck for restricting the further improvement of the performance of the pixel sensor. A pixel front-end circuit that can solve the above-mentioned problems is needed. Disclosure of Invention The application aims to provide a pixel front-end circuit, a pixel sensor and a detector system, so that the pixel front-end circuit can meet the requirements of low power consumption, high uniformity and high detection performance in a limited area. In order to achieve the above object, the present application provides the following. In a first aspect, the application provides a pixel front-end circuit comprising an input stage, a charge transfer amplifying branch, a bias and baseline setting network, and a discrimination output stage and a second cascode shielding module; The input stage and the charge transfer amplifying branch circuit comprise a source electrode follower tube, a first cascode shielding tube, a load current source and a current feedback network, wherein the current feedback network comprises a feedback capacitor, a first feedback transistor and a second feedback transistor; the bias and baseline setting network comprises a main bias current tube and a threshold current and baseline restoration circuit, wherein the threshold current and baseline restoration circuit comprises a first feedback transistor and a second feedback transistor; the judging output stage and the second cascode shielding module comprise a load tube, a second cascode shielding tube and an input tube. In an embodiment, in the input stage and the charge transfer amplifying branch, a gate of the source follower transistor is connected with an input node, a source of the source follower transistor is connected with a charge transfer node, the input node is directly connected with an N-type collecting well ohmic contact of a sensor to receive collected charges of the N-type collecting well, a source of the first cascode shielding transistor is connected with a drain of the source follower transistor, a drain of the first cascode shielding transistor is connected with a first stage output node, a gate of the first cascode shielding transistor is connected with a first PMOS bias voltage, a source of the load current source transistor is grounded, a drain of the load current source transistor is connected with a first stage output node, a gate of the load current source transistor is connected with a feedback node, one end of the feedback capacitor is connected with the charge transfer node, the other end of the feedback capacitor, the drain of the first feedback transistor and the drain of the second feedback transistor are all connected with a feedback node, a gate of the first feedback transistor is connected with a second PMOS bias voltage, a gate of the first feedback transistor is connected with a first stage output voltage, and a source of the first feedback transistor is connected with a first stage