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CN-121985468-A - Differential signal Fanout structure for improving high-speed signal integrity

CN121985468ACN 121985468 ACN121985468 ACN 121985468ACN-121985468-A

Abstract

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving high-speed signal integrity, which comprises a PCB substrate, a differential signal pair arranged on the PCB substrate, and a grounding shielding unit, wherein the differential signal pair comprises a P signal wire and an N signal wire which are respectively used for connecting chip pins. The invention obviously reduces the crosstalk of high-speed differential signals by adopting a design of decoupling the layered fan-out and the large spacing, breaks through the limitation that the traditional Fanout structure is required to be tightly coupled and wired on the same layer, respectively distributes P signals and N signals on the surface layer and the inner layer of the PCB, realizes the maximization of the horizontal projection spacing (forming a decoupling spacing area) by utilizing the isolation of the vertical space, obviously reduces the coupling capacitance between wires, obviously reduces the far-end crosstalk, and improves the signal-to-noise ratio and the eye pattern opening of the high-speed link.

Inventors

  • ZHAO TIANYU
  • WANG GUOGUO

Assignees

  • 苏州芯创连光电科技有限公司

Dates

Publication Date
20260505
Application Date
20251219

Claims (10)

  1. 1. A differential signal Fanout architecture that promotes high-speed signal integrity, comprising: A PCB substrate (100); The differential signal pair is arranged on the PCB substrate (100) and comprises a P signal wire (10) and an N signal wire (20), and the P signal wire (10) and the N signal wire (20) are respectively used for connecting chip pins; and a ground shield unit including a ground reference plane and a plurality of ground vias (30) distributed on the PCB substrate (100); In the fan-out area of the Fanout structure, the P signal wire (10) and the N signal wire (20) are positioned on different signal layers in the vertical direction, and form a decoupling interval area in the horizontal projection direction, wherein the width of the decoupling interval area is larger than the conventional differential coupling interval; the plurality of grounding through holes (30) are arranged on two outer sides of the differential signal pair, and the plurality of grounding through holes (30) are also arranged in a decoupling interval area between the P signal wire (10) and the N signal wire (20) and are used for forming a three-dimensional shielding loop around the P signal wire (10) and the N signal wire (20).
  2. 2. The differential signal Fanout structure for improving high-speed signal integrity of claim 1, wherein said P signal trace (10) is disposed on a surface layer of a PCB substrate (100); The N signal wires (20) are connected to an inner layer signal layer of the PCB substrate (100) through blind holes (21) in a layer-changing mode, and at least one grounding reference plane is arranged between the inner layer signal layer and the surface layer at intervals; the width d of the decoupling space region satisfies a decoupling condition to reduce an electromagnetic coupling effect between the P signal trace (10) and the N signal trace (20).
  3. 3. A differential signal Fanout structure for improving high-speed signal integrity according to claim 1, characterized in that the layout of a plurality of said ground vias (30) satisfies the following condition: The grounding via hole (30) forms an enclosing structure around the P signal wire (10) and the N signal wire (20); The center-to-center spacing between adjacent ground vias (30) is less than or equal to one twentieth of the wavelength lambda corresponding to the signal transmission frequency; The edge distance of the grounding via hole (30) from the edge of the P signal wire (10) or the N signal wire (20) is less than or equal to 25 micrometers.
  4. 4. The differential signal Fanout structure of claim 2, wherein the width d of said decoupling pitch region is determined according to the formula: d≥k×( / ) Wherein k is a safety coefficient, Is the coupling capacitance between the wires, Is the total capacitance of the signal line to ground.
  5. 5. The structure of differential signal Fanout for improving high-speed signal integrity according to claim 1, wherein the line widths of said P signal trace (10) and N signal trace (20) are independently calibrated to control differential impedance within a range of 90Ω+ -5%.
  6. 6. The differential signal Fanout structure for improving high-speed signal integrity according to claim 1, wherein a shorter physical length of said P signal trace (10) or N signal trace (20) is provided with a serpentine wire-wrap structure due to a difference in length caused by layered routing; The winding distance of the serpentine winding structure is larger than or equal to 3 times of line width, and the delay deviation in the differential signal pair is controlled to be smaller than 5ps.
  7. 7. The differential signal Fanout structure for improving high speed signal integrity of claim 1, wherein said Fanout structure is adapted to a BGA packaged chip having a pin pitch of 0.8mm, a trace pitch of said Fanout structure is set to be 150 microns or more, and an aperture of said ground via (30) is 0.1mm.
  8. 8. The differential signal Fanout structure of claim 1, further comprising a termination resistor disposed at an end of the signal, wherein the termination resistor has a resistance of 50Ω for reducing reflection noise.
  9. 9. A method of designing a differential signal Fanout structure for improving high speed signal integrity as claimed in any one of claims 1-8, comprising the steps of: S1, obtaining the transmission rate of differential signals and parameters of the PCB, and obtaining the transmission rate of the differential signals and the parameters of the PCB according to a formula d not less than k× @ / ) Calculating the minimum safety distance; S2, adopting a layered wiring strategy, arranging P signals in a differential pair on a surface layer, leading N signals to an inner layer through a via hole, and enabling the horizontal projection distance between the P signals and the N signals to meet the minimum safety distance; step S3, densely arranging grounding via holes between and around the P signal and the N signal to generate a grounding via hole array, and ensuring that the spacing between the grounding via holes is less than or equal to lambda/20; and S4, performing impedance matching calibration on the signal wiring, and adding a snake-shaped winding on the shorter signal wiring to perform time delay compensation.
  10. 10. A high-speed optical communication module, comprising a PCB main board and a high-speed signal processing chip mounted on the PCB main board, wherein the PCB main board adopts the differential signal Fanout structure for improving the high-speed signal integrity according to any one of claims 1 to 8, and is used for transmitting differential signals with a rate of 112Gbps or more.

Description

Differential signal Fanout structure for improving high-speed signal integrity Technical Field The invention belongs to the technical field of electronic circuit design, and particularly relates to a differential signal Fanout structure for improving high-speed signal integrity. Background With the massive application of high-speed interfaces in data centers, high-speed optical communication, servers and other devices, the transmission rate of differential signals on a printed circuit board is continuously improved, and the single channel rate of interfaces such as PCIe, serDes, DDR can reach tens of Gbps or even higher. In such high-speed differential interfaces, the chip is usually packaged in a high-density package such as a BGA, and the pin area of the chip needs to lead out the P-terminal and N-terminal pads to the PCB trace layer through a differential signal Fanout structure. Because BGA pin interval is smaller, traditional Fanout structure adopts the mode of closely arranging P/N differential line in parallel on same signal layer generally, and differential line interval is mainly limited by encapsulation pin interval and wiring density, is difficult to show the increase in fan-out area, can lead to on the one hand that electromagnetic coupling between the inside P/N signal of differential pair is stronger, and on the other hand parallel section between the adjacent differential pair is longer, also easily produces obvious near-end crosstalk and far-end crosstalk, can cause signal integrity problems such as eye pattern closure and error rate rising under high-speed scene. In the prior art, a part of Fanout design scheme tries to arrange a plurality of grounding through holes or enlarge local copper outside a differential pair so as to improve a return current path, but the grounding through holes are concentrated outside the differential pair, an effective grounding shielding structure is usually lacking between a P signal line and an N signal line, meanwhile, the grounding surface layer near the Fanout area can also have discontinuous conditions such as slotting, hollowness and the like, so that the offset of a return current path and the discontinuous local impedance are caused, and the high-frequency noise coupling and the crosstalk between the differential pair are difficult to be fully restrained; and with the further improvement of the working speed, the conventional Fanout structure based on close-coupled multi-layer wiring and supplemented with a small amount of grounding through holes has the difficulty in considering the internal decoupling of the differential pair and the integrity of a grounding loop while ensuring the high-density wire outgoing of the chip pins. Disclosure of Invention The present invention is directed to a differential signal Fanout structure for improving high-speed signal integrity, which solves the above-mentioned problems. In order to achieve the above purpose, the present invention provides a differential signal Fanout structure for improving the integrity of high-speed signals, comprising: A PCB substrate; The differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting with a chip pin; The grounding shielding unit comprises a grounding reference plane and a plurality of grounding through holes which are distributed on the PCB substrate; In the fan-out area of the Fanout structure, the P signal wiring and the N signal wiring are located on different signal layers in the vertical direction, and form a decoupling interval area in the horizontal projection direction, wherein the width of the decoupling interval area is larger than the conventional differential coupling interval; The plurality of grounding through holes are arranged on two outer sides of the differential signal pair, and are also arranged in a decoupling interval area between the P signal wire and the N signal wire and used for forming a three-dimensional shielding loop around the P signal wire and the N signal wire. Preferably, the P signal wiring is arranged on the surface layer of the PCB substrate; the N signal wires are connected to an inner signal layer of the PCB substrate through blind hole layer replacement, and at least one grounding reference plane is arranged between the inner signal layer and the surface layer at intervals; The width d of the decoupling interval region meets the decoupling condition so as to reduce the electromagnetic coupling effect between the P signal wiring and the N signal wiring. Preferably, the layout of the plurality of ground vias satisfies the following condition: The grounding via forms an enclosure structure around the P signal wire and the N signal wire; the center-to-center spacing between adjacent ground vias is less than or equal to one twentieth of the wavelength lambda corresponding to the signal transmission frequency; The edge distance of the grounding via is