CN-121985488-A - Structure and layout method for chip connection DDR based on front and back pastes

Abstract

The application provides a structure and a layout method for connecting Double Data Rate (DDR) by chips based on positive and negative pastes, which are characterized in that holes are punched in the central positions of 4 PIN PINs with adjacent relation or the allowable deviation range deviating from the central positions on DDR particles, the holes are punched in the adjacent relation, so that the high-density integration of the holes on the DDR particles is ensured, and all devices are connected through the holes, thereby being indirectly beneficial to the integration of the devices on a Printed Circuit Board (PCB). And because the DDR particle PIN foot and the chip PIN foot contacted with the same through hole have the same network attribute, different networks can be realized without interference only by adjusting the through hole position, and the quality of the chip and DDR particle communication is ensured. And the chip PIN PINs with the same network attribute and the DDR particle PIN cannot be in short circuit, so that the distance between the through holes can be unlimited, and the high-density integration of the PCB device is realized.

Inventors

• ZHANG HAITAO
• HE SHAOJIE
• SHEN JIAN

Assignees

• 云尖信息技术股份有限公司

Dates

Publication Date

20260505

Application Date

20251219

Claims (10)

1. 1. The layout method of the chip connection DDR based on the front and back pastes is characterized by comprising the following steps: s1, placing a chip and DDR particles on a first surface and a second surface of a PCB respectively, wherein the first surface and the second surface are opposite; s2, fan-out punching is conducted on the DDR particles; S3, judging whether the chip PIN PINs projected on the fan-out punching area are contacted with the DDR via holes punched in the punching area, If yes, defining the network attribute of the chip PIN PIN and the network attribute of the DDR via hole contacted with the chip PIN PIN as the same; if not, the network attribute undefined mark is carried out on the chip PIN.
2. 2. The method for layout of chip attach DDR based on front-back paste of claim 1, further comprising the step of: s4, judging whether the DDR via hole realizes that different networks do not interfere, If yes, marking the DDR via hole as qualified in punching; if not, turning to step S5 or jumping to step S6; s5, adjusting the DDR via hole position, and returning to the step S4.
3. 3. The method for layout of chip attach DDR based on front-back paste of claim 2, wherein step S6 comprises the steps of: s61, screening out the network attribute closest to the DDR via hole as the interconnection mode of a power supply network or a ground network to change the DDR via hole; s62, adjusting the interconnection mode to change the type of the DDR via hole into a blind hole, or directly connecting the DDR via hole with a metal surface layer, wherein the network property of the metal surface layer is a power supply network.
4. 4. The front-back paste based chip connection DDR layout method of claim 1, wherein said second side is within a projected area of said first side.
5. 5. The method for layout of chip connection DDR based on front-back bonding of claim 1, wherein said second surface is a back surface of said PCB board and said first surface is a front surface of the same PCB board.
6. 6. The method for layout of chip connection DDR based on front-back paste according to claim 1, wherein in step S2, the method for fan-out punching the DDR particles is as follows: and punching the central sites of the 4 PIN PINs on the DDR particles, which are in adjacent relation with each other, or the allowable deviation range from the central sites, wherein the punched holes are defined as DDR through holes.
7. 7. The method of claim 1, wherein the network attributes include one or more of a power network, a ground network, and a signal network.
8. 8. The front-back paste based chip connect DDR layout method of claim 1, wherein said DDR particles comprise LPDDR5.
9. 9. A framework for connecting DDR (double data rate) by chips based on positive and negative adhesion is characterized in that chips and DDR particles are respectively placed on a first surface and a second surface of a PCB (printed circuit board), the first surface and the second surface are oppositely arranged, a chip PIN is contacted with a DDR via hole perforated on the DDR particles, and the network attribute of the chip PIN is the same as that of the released DDR via hole.
10. 10. The architecture for connecting DDR based on front and back paste chips as defined in claim 9, wherein when a first DDR via is subjected to network interference, the type of a second DDR via closest to the first DDR via is adjusted to be a blind via, or the first DDR via with network attribute of power supply network is directly connected with a metal surface layer; And the DDR via holes are punched in the central loci of 4 PIN PINs which are adjacent to each other on the DDR particles or the allowable position deviation range deviating from the central loci.

Description

Structure and layout method for chip connection DDR based on front and back pastes Technical Field The application relates to the technical field of integrated circuits, in particular to a framework and a layout method for connecting DDR (double data rate) with a main chip based on positive and negative pastes. Background In recent years, industry technology development requires smaller and smaller areas of PCBs (printed circuit boards), more and more devices (e.g., chips) are integrated thereon, smaller and smaller inter-chip pitches, and densities are increased. In order to meet the design requirements of low-cost and high-density PCB boards, the layout and wiring space of chips and DDR particles (memory particles) is gradually reduced, so how to perform low-cost and high-density layout and wiring on a limited PCB size is particularly important. In the existing method, a positive and negative paste design exists between the chip and the DDR particles, but the layout and wiring interconnection are usually carried out through blind holes and blind holes. The mode needs multiple pressing and electroplating, is complex in design, long in period and high in cost. In another conventional method, DDR particles are laid out at the peripheral positions of chips on the same side, and the layout wiring interconnection is performed through vias or deep micro-holes. However, the method has low device layout density, and the layout wiring interconnection scheme is not generally applicable to a PCB with very limited size. Disclosure of Invention The application aims to realize high-density and low-cost layout of chips and DDR particles on a PCB, and provides a structure and a layout method for connecting chips with DDR based on positive and negative adhesion. To achieve the purpose, the application adopts the following technical scheme: The layout method of the chip connection DDR based on the positive and negative pastes comprises the following steps: s1, placing a chip and DDR particles on a first surface and a second surface of a PCB respectively, wherein the first surface and the second surface are opposite; s2, fan-out punching is conducted on the DDR particles; S3, judging whether the chip PIN PINs projected on the fan-out punching area are contacted with the DDR via holes punched in the punching area, If yes, defining the network attribute of the chip PIN PIN and the network attribute of the DDR via hole contacted with the chip PIN PIN as the same; if not, the network attribute undefined mark is carried out on the chip PIN. Preferably, the layout method of the chip connection DDR based on the front and back paste further comprises the steps of: s4, judging whether the DDR via hole realizes that different networks do not interfere, If yes, marking the DDR via hole as qualified in punching; if not, turning to step S5 or jumping to step S6; s5, adjusting the DDR via hole position, and returning to the step S4. Preferably, step S6 comprises the steps of: s61, screening out the network attribute closest to the DDR via hole as the interconnection mode of a power supply network or a ground network to change the DDR via hole; s62, adjusting the interconnection mode to change the type of the DDR via hole into a blind hole, or directly connecting the DDR via hole with a metal surface layer, wherein the network property of the metal surface layer is a power supply network. Preferably, the second face is within the projected area of the first face. Preferably, the second surface is a back surface of the PCB board, and the first surface is a front surface of the same PCB board. Preferably, in step S2, the method for performing fan-out punching on the DDR particles includes: and punching the central sites of the 4 PIN PINs on the DDR particles, which are in adjacent relation with each other, or the allowable deviation range from the central sites, wherein the punched holes are defined as DDR through holes. Preferably, the network attribute includes one or more of a power network, a ground network, and a signal network. Preferably, the DDR particles comprise LPDDR5. The application also provides a structure for connecting the DDR by the chip based on the positive and negative adhesion, wherein the chip and the DDR particles are respectively arranged on the first surface and the second surface of the PCB, the first surface and the second surface are oppositely arranged, the chip PIN is contacted with the DDR via hole perforated on the DDR particles, and the network property of the chip PIN is the same as that of the released DDR via hole. Preferably, when network interference occurs in the first DDR via hole, adjusting the type of a second DDR via hole closest to the first DDR via hole to be a blind hole, or directly connecting the first DDR via hole with a network attribute of a power supply network by using a metal surface layer; And the DDR via holes are punched in the central loci of 4 PIN PINs which are adjacent to each oth