CN-121985529-A - Process integration method for improving yield of SRAM (static random Access memory) area

CN121985529ACN 121985529 ACN121985529 ACN 121985529ACN-121985529-A

Abstract

The invention discloses a process integration method for improving the yield of an SRAM region, which comprises the following steps: step one, providing a semiconductor substrate with a pseudo gate structure, wherein a contact hole etching barrier layer covers the top surface, the side surface and the outer surface of the pseudo gate structure. And secondly, forming a first interlayer film, wherein part of the gate interval region is not completely filled and is provided with a closed cavity, the size of the cavity is related to the thickness of the first interlayer film deposition and the contact hole etching barrier layer, and when the capacities of the SRAM are different, the technological conditions of the first interlayer film deposition and the contact hole etching barrier layer are kept unchanged, and the technological integration of the SRAM with different capacities is realized. And thirdly, performing the first CMP stopped at the contact hole etching barrier layer. And step four, forming a second interlayer film. And fifthly, stopping the second CMP at the polysilicon gate. The invention can realize the process integration of SRAM with different capacities and improve the yield.

Inventors

TIAN ZHI
CAO YURONG
CHEN HAOYU
SHAO HUA

Assignees

上海华力集成电路制造有限公司

Dates

Publication Date: 20260505
Application Date: 20260120

Claims (14)

1. A process integration method for improving yield of an SRAM region, comprising: Providing a semiconductor substrate, forming a pseudo gate structure on the surface of a selected area of the semiconductor substrate, wherein the pseudo gate structure comprises a first gate dielectric layer, a polysilicon gate and a hard mask layer which are sequentially overlapped; Performing first interlayer film deposition to form a first interlayer film, wherein part of the gate interval region is completely filled, part of the gate interval region is not completely filled, a closed cavity is formed in the first interlayer film, and the depth-to-width ratio of the gate interval region with the cavity is larger than that of the completely filled gate interval region; The size of the cavity is related to the thickness of the first interlayer film deposition and the contact hole etching barrier layer, and when the SRAM capacity is different, the process conditions of the first interlayer film deposition and the process conditions of the contact hole etching barrier layer are kept unchanged, so that the process conditions of the first interlayer film deposition and the process conditions of the contact hole etching barrier layer are prevented from being changed for eliminating the cavity, and the process integration of the SRAM with different capacities is realized; Step three, performing first CMP (chemical mechanical polishing) on the first interlayer film, wherein the first CMP stops at the contact hole etching barrier layer, and the cavity is exposed after the first CMP; step four, performing second interlayer film deposition to form a second interlayer film, wherein the second interlayer film can completely fill the cavity, and a third interlayer film is formed by overlapping the first interlayer film and the second interlayer film; And fifthly, performing second CMP (chemical mechanical polishing) on the third interlayer film, wherein after the second CMP, the third interlayer film which is exposed out of the top surface of the polysilicon gate and remains completely fills the gate interval region so as to improve the yield of the SRAM region.
2. The process integration method for improving SRAM area yield of claim 1, further comprising: step six, removing the polysilicon gate; And step seven, forming a metal gate in the polysilicon gate removing area.
3. The process integration method of claim 1, wherein the semiconductor substrate comprises a silicon substrate.
4. The process integration method for improving the yield of the SRAM region of claim 2, wherein in step six, the first gate dielectric layer is removed or reserved; when the first gate dielectric layer is removed in the step six, the step seven of forming the metal gate further includes a step of forming a second gate dielectric layer before forming the metal gate.
5. The method of claim 1, wherein the hard mask layer comprises silicon nitride and/or silicon oxide.
6. The process integration method of claim 1, wherein the contact etch stop layer material comprises silicon nitride.
7. The process integration method for improving the yield of the SRAM region of claim 1, wherein a sidewall is further formed on the side of the dummy gate structure.
8. The process integration method for improving SRAM area yield of claim 1, wherein shallow trench isolations are further formed on said semiconductor substrate, and an active region is formed by said semiconductor substrate between said shallow trench isolations; in the second step, the size of the cavity is also related to the step height of the shallow trench isolation, and when the SRAM capacity is different, the process condition of the shallow trench isolation is kept unchanged.
9. The process integration method for improving the yield of an SRAM region of claim 1, wherein NMOS and PMOS are formed simultaneously in the SRAM region; forming embedded SiGe epitaxial layers in the semiconductor substrate at two sides of the pseudo gate structure of the PMOS; The process of forming the embedded SiGe epitaxial layer causes a loss in the thickness of the hard mask layer on top of the dummy gate structure of the PMOS.
10. The process integration method for improving the yield of an SRAM region of claim 4, wherein in step six, the material of the first gate dielectric layer comprises a high dielectric constant material when the first gate dielectric layer remains, or wherein in step six, the material of the second gate dielectric layer formed in step seven comprises a high dielectric constant material when the first gate dielectric layer is removed.
11. The process integration method for improving SRAM area yield of claim 2, wherein in step seven, the metal gate comprises a work function metal layer and a metal conductive material layer; The work function metal layer comprises a P-type work function metal layer and an N-type work function metal layer.
12. The method of claim 11, wherein in step seven, the P-type work function metal layer is formed; removing the P-type work function metal layer in the NMOS forming region; Forming the N-type work function metal layer; Filling the metal conductive material layer.
13. The method of claim 11, wherein the material of the P-type work function metal layer comprises TiN.
14. The method for improving the yield of an SRAM region of claim 9, wherein in step one, before the contact hole etching barrier layer is formed, further comprising: And (5) performing a photoresist back etching process.

Description

Process integration method for improving yield of SRAM (static random Access memory) area Technical Field The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a process integration method for improving yield of an SRAM region. Background The OLED is of the current-driven type, and the current density of the OLED depends on the driving voltage across the OLED, the higher the voltage, the greater the current density. The OLED device itself ages during long periods of use, and the relationship between its voltage, current density, and luminance is not always constant. Aging of the OLED device is most directly manifested by an increase in the OLED turn-on voltage and a decrease in the light emitting efficiency. In order to maintain the same light emission luminance, it is necessary to increase the OLED current flowing therethrough, so that a high voltage device is required in the OLED to realize a function of a large current. The 22HV is compatible with these processes and has a large SRAM capacity, which causes a short circuit between two nodes between NMOS of adjacent cells due to metal gate filling, which is caused by insufficient filling capability of an interlayer dielectric layer, that is, an interlayer film, in the region of the SRAM, thereby causing yield failure. With further progress of process nodes, the size of a device in the SRAM is smaller, the surface area of polysilicon of the SRAM with the same capacity is larger, so that the thickness of the contact hole etching barrier layer is greatly fluctuated, and due to the fact that a hard mask on a polysilicon gate is etched out of a PMOS region in silicon germanium, the depth-to-width ratio under the same width is smaller than that of NMOS, cavities caused by subsequent interlayer dielectric layer filling are unlikely to occur. In the prior art, the interlayer dielectric layer is chemically and mechanically ground and then stops on the polysilicon layer, namely the polysilicon gate, and the polysilicon gate is connected with the contact hole when the subsequent metal gate is filled. The area formed by the cavity is related to the step height of isolation silicon oxide of the front layer, namely shallow trench isolation, the thickness of the contact hole etching barrier layer of the front layer and the filling capacity of the interlayer dielectric layer, and if the area is adjusted according to the capacity of the SRAM, multiple processes of integrated development are required for each product. As shown in fig. 1, which is a flow chart of a manufacturing method of a conventional SRAM, fig. 1 shows a flow chart between a filling process of an interlayer film between dummy gate structures and a replacement process of a metal gate, and as shown in fig. 2A to 2D, which is a schematic view of a device structure in each step of the manufacturing method of the conventional SRAM, the manufacturing method of the conventional SRAM includes: and step S101, a photoresist back etching Process (PREB) for removing the hard mask layer on the top of the polysilicon gate 106. As shown in fig. 2A, first, a semiconductor substrate 101 needs to be provided, a dummy gate structure 104 is formed on a surface of a selected area of the semiconductor substrate 101, the dummy gate structure 104 includes a first gate dielectric layer 105, a polysilicon gate 106 and a hard mask layer sequentially stacked, a contact hole etching barrier layer 110 covers a top surface and a side surface of the dummy gate structure 104 and a surface outside the dummy gate structure 104, and a gate spacer is provided between the dummy gate structures 104. A sidewall 108 is also formed on the side of the dummy gate structure 104. In fig. 2A, the sidewall 108 includes three layers, i.e., a silicon nitride sidewall, a silicon oxide sidewall, and a silicon nitride sidewall. Shallow trench isolations 103 are also formed on the semiconductor substrate 101, with active regions formed by the semiconductor substrate 101 between the shallow trench isolations 103. NMOS and PMOS are formed simultaneously in the SRAM region, and an embedded SiGe epitaxial layer is formed in the semiconductor substrate 101 on both sides of the dummy gate structure 104 of the PMOS. The process of forming the embedded SiGe epitaxial layer causes a loss in the thickness of the hard mask layer on top of the dummy gate structure 104 of the PMOS. In fig. 2A, the formation region of NMOS in the SRAM region is shown, and two of the dummy gate structures 104 shown in fig. 2A correspond to one NMOS, respectively. In the NMOS formation region, a P-type well 102 is also formed in the semiconductor substrate 101. The material of the first gate dielectric layer 105 includes a high dielectric constant material. An interface layer 107 is further formed at the bottom of the first gate dielectric layer 105, and the interface layer 107 is typically formed by oxidizing the surface o