CN-121985530-A - Technological method for improving yield of transistor, transistor and semiconductor memory

Abstract

The technological method for improving the yield of the transistor, the transistor and the semiconductor memory comprise the steps of forming a first grid electrode layer on a silicon substrate, forming a second grid electrode on one side, away from the silicon substrate, of the first grid electrode layer, forming a first oxide layer on the second grid electrode along the direction parallel to the plane of the silicon substrate, performing chemical vapor deposition on the first oxide layer by using tetraethoxysilane, etching the first oxide layer to form a first oxide retaining wall, wherein the first oxide retaining wall at least covers the side wall of the second grid electrode, and completing manufacturing of other parts of the transistor. Silicon dioxide thin films formed by tetraethoxysilane deposition can not generate silicon particles, so that defects in the manufacturing process of transistors and wafers can be effectively reduced, the wafer yield is improved, and the probability of abnormal memory cells is reduced.

Inventors

• ZHANG YANYAN
• LIU ZHAO
• HUANG JINHUANG

Assignees

• 北京紫光青藤微系统有限公司

Dates

Publication Date

20260505

Application Date

20260127

Claims (10)

1. 1. A process for improving the yield of a transistor, comprising: forming a first gate layer on a silicon substrate; forming a second gate layer on one side of the first gate layer, which is away from the silicon substrate, and etching the second gate layer to form a second gate; Etching the first oxide layer so as to form a first oxide retaining wall on at least one side of the second grid in a direction parallel to the plane of the silicon substrate, wherein the first oxide retaining wall at least covers the side wall of the second grid; And finishing the manufacture of other parts of the transistor.
2. 2. The process for improving the yield of a transistor according to claim 1, wherein, the reaction formula for forming the first oxide layer using tetraethoxysilane includes: 。
3. 3. The method of claim 1, further comprising forming a first nitride layer on a side of the first oxide wall away from the second gate electrode, etching the first nitride layer such that a first nitride wall is formed on at least one side of the first oxide wall away from the second gate electrode in a direction parallel to a plane of the silicon substrate; Forming a second oxide layer on one side of the first nitride retaining wall away from the second grid electrode; and etching the second oxide layer and the first grid electrode layer to form a first grid electrode.
4. 4. The method of claim 3, wherein the second oxide layer is formed by chemical vapor deposition using tetraethoxysilane.
5. 5. The method of claim 3, wherein the first side of the first gate and the second side of the first nitride retaining wall are on the same side of the second gate in a direction parallel to the plane of the silicon substrate, and wherein the first side and the second side are flush in a direction perpendicular to the plane of the silicon substrate.
6. 6. The method of claim 3, further comprising forming a third gate on one side of the first gate and the second gate in a direction parallel to the plane of the silicon substrate, and forming a fourth gate on the other side.
7. 7. The method of claim 6, wherein a third oxide layer is formed over the first nitride layer prior to forming the third and fourth gates, the third oxide layer encapsulating the first nitride layer and at least a portion of sidewalls of the first gate; at least part of the third oxide layer is positioned between the third grid electrode and the first grid electrode and the second grid electrode, and at least part of the third oxide layer is positioned between the fourth grid electrode and the first grid electrode and the second grid electrode.
8. 8. A transistor is characterized by being manufactured by adopting the process method for improving the yield of the transistor according to any one of claims 1-7, comprising a silicon substrate, a first grid electrode, a second grid electrode, a first oxide retaining wall and a first nitride retaining wall, wherein the second grid electrode is positioned at one side of the first grid electrode, which is away from the silicon substrate, in the direction perpendicular to the plane of the silicon substrate; The first side face of the first grid electrode and the second side face of the first nitride retaining wall are positioned on the same side of the second grid electrode in the direction parallel to the plane of the silicon substrate, and the first side face and the second side face are flush in the direction perpendicular to the plane of the silicon substrate.
9. 9. The transistor of claim 8, further comprising a third gate and a fourth gate, the third gate being located on one side of the first gate and the second gate and the fourth gate being located on the other side of the first gate and the second gate in a direction parallel to a plane in which the silicon substrate lies.
10. 10. A semiconductor memory comprising a transistor according to any one of claims 8-9.

Description

Technological method for improving yield of transistor, transistor and semiconductor memory Technical Field The present disclosure relates to the field of semiconductor wafer manufacturing, and more particularly, to a process method for improving yield of a transistor, and a semiconductor memory. Background In the process of manufacturing a semiconductor wafer containing a memory cell, a silicon oxide film layer is generally manufactured by adopting silane nitroso to deposit a silicon dioxide film, but the silicon dioxide is generated by adopting silane nitroso, and meanwhile, some side reactions generate solid tiny silicon particles, which are difficult to remove and fall into a transistor to form defects, so that the wafer yield is lower, and the memory cell is abnormal. Therefore, how to reduce internal defects of the transistor, improve the wafer yield, and reduce the probability of memory cell abnormality is a technical problem to be solved by those skilled in the art. Disclosure of Invention In order to solve the technical problems, the disclosure provides a process method for improving the yield of a transistor, the transistor and a semiconductor memory, which are used for reducing internal defects of the transistor, improving the yield of a wafer and reducing the probability of abnormal memory cells. The invention provides a process method for improving the yield of a transistor, which comprises the steps of forming a first grid electrode layer on a silicon substrate, forming a second grid electrode layer on one side, away from the silicon substrate, of the first grid electrode layer, etching the second grid electrode layer to form a second grid electrode, forming a first oxide layer on the second grid electrode, performing chemical vapor deposition on the first oxide layer by using tetraethoxysilane, etching the first oxide layer to form a first oxide retaining wall on at least one side of the second grid electrode in a direction parallel to the plane of the silicon substrate, wherein the first oxide retaining wall at least covers the side wall of the second grid electrode, and completing the manufacture of other parts of the transistor. Optionally, the reaction formula for forming the first oxide layer using tetraethoxysilane includes: 。 optionally, continuing to form a first nitride layer on one side of the first oxide retaining wall away from the second gate, and etching the first nitride layer so as to form a first nitride retaining wall on at least one side of the first oxide retaining wall away from the second gate in a direction parallel to a plane in which the silicon substrate is located; Forming a second oxide layer on one side of the first nitride retaining wall away from the second grid electrode; and etching the second oxide layer and the first grid electrode layer to form a first grid electrode. Optionally, the second oxide layer is formed by chemical vapor deposition using tetraethoxysilane. Optionally, along a direction parallel to the plane of the silicon substrate, in a direction parallel to the plane of the silicon substrate, the first side surface of the first gate and the second side surface of the first nitride retaining wall are located on the same side of the second gate, and in a direction perpendicular to the plane of the silicon substrate, the first side surface and the second side surface are flush. Optionally, a third gate is formed on one side of the first gate and the second gate along a direction parallel to the plane of the silicon substrate, and a fourth gate is formed on the other side. Optionally, forming a third oxide layer on the first nitride layer before forming the third gate and the fourth gate, the third oxide layer cladding the first nitride layer and at least part of the sidewalls of the first gate; at least part of the third oxide layer is positioned between the third grid electrode and the first grid electrode and the second grid electrode, and at least part of the third oxide layer is positioned between the fourth grid electrode and the first grid electrode and the second grid electrode. Based on the same inventive concept, the present disclosure provides a transistor manufactured by adopting the process method for improving the yield of the transistor, comprising a silicon substrate, a first grid electrode, a second grid electrode, a first oxide retaining wall and a first nitride retaining wall, wherein the second grid electrode is positioned at one side of the first grid electrode, which is away from the silicon substrate, in a direction perpendicular to a plane of the silicon substrate, and the first nitride retaining wall is positioned at least one side of the first oxide retaining wall, which is away from the second grid electrode, in a direction parallel to the plane of the silicon substrate; The first side face of the first grid electrode and the second side face of the first nitride retaining wall are positioned on the same side of the second