CN-121985531-A - Semiconductor device and method for manufacturing the same

Abstract

The embodiment of the disclosure discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first memory chip including a first transistor including a first active region in a first semiconductor layer and a first gate structure on a first side of the first semiconductor layer, a first conductive structure extending through the first semiconductor layer and a first dielectric layer covering the first transistor in a thickness direction of the first semiconductor layer and connected to a source of the first active region, and a second conductive structure extending through the first dielectric layer and the first semiconductor layer in the thickness direction of the first semiconductor layer and connected to a drain of the first active region.

Inventors

• LIU XIAOXIN

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260505

Application Date

20241025

Claims (20)

1. 1. A semiconductor device is characterized in that the semiconductor device comprises a first memory chip, and the first memory chip comprises: a first transistor including a first active region in a first semiconductor layer and a first gate structure on a first side of the first semiconductor layer; A first conductive structure extending through the first semiconductor layer and a first dielectric layer covering the first transistor in a thickness direction of the first semiconductor layer and connected with a source of the first active region; And a second conductive structure extending through the first dielectric layer and the first semiconductor layer in a thickness direction of the first semiconductor layer and connected with the drain electrode of the first active region.
2. 2. The semiconductor device according to claim 1, wherein the first memory chip further comprises: A first gate contact portion extending through the first dielectric layer in a thickness direction of the first semiconductor layer and connected to the first gate structure; And the third conductive structure extends through the first dielectric layer and the first semiconductor layer along the thickness direction of the first semiconductor layer, wherein the third conductive structure is connected with the first gate contact part through a conductive layer, and the conductive layer is positioned on one side of the first dielectric layer relatively far from the first semiconductor layer.
3. 3. The semiconductor device of claim 2, wherein the first conductive structure comprises a first contact and a first connection, wherein the first contact and the first connection extend through the first dielectric layer and the first semiconductor layer, respectively; The second conductive structure comprises a second contact part and a second connection part, wherein the second contact part and the second connection part respectively extend through the first dielectric layer and the first semiconductor layer; the third conductive structure includes a third contact portion and a third connection portion, wherein the third contact portion and the third connection portion extend through the first dielectric layer and the first semiconductor layer, respectively.
4. 4. The semiconductor device according to claim 3, wherein dimensions of the first contact portion, the second contact portion, and the third contact portion in a thickness direction of the first semiconductor layer are substantially the same.
5. 5. The semiconductor device according to claim 3, wherein dimensions of the first connection portion, the second connection portion, and the third connection portion in a thickness direction of the first semiconductor layer are substantially the same.
6. 6. The semiconductor device according to claim 3, wherein a cross-sectional dimension of the first contact portion at a surface relatively close to the first semiconductor layer is smaller than or equal to a cross-sectional dimension of the first contact portion at a surface relatively far from the first semiconductor layer, wherein a cross-sectional dimension of the second contact portion at a surface relatively close to the first semiconductor layer is smaller than or equal to a cross-sectional dimension of the second contact portion at a surface relatively far from the first semiconductor layer, and wherein a cross-sectional dimension of the third contact portion at a surface relatively close to the first semiconductor layer is smaller than or equal to a cross-sectional dimension of the third contact portion at a surface relatively far from the first semiconductor layer.
7. 7. The semiconductor device according to claim 3, wherein a cross-sectional dimension of the first connection portion at a surface relatively close to the first dielectric layer is smaller than or equal to a cross-sectional dimension of the first connection portion at a surface relatively far from the first dielectric layer, wherein a cross-sectional dimension of the second connection portion at a surface relatively close to the first dielectric layer is smaller than or equal to a cross-sectional dimension of the second connection portion at a surface relatively far from the first dielectric layer, and wherein a cross-sectional dimension of the third connection portion at a surface relatively close to the first dielectric layer is smaller than or equal to a cross-sectional dimension of the third connection portion at a surface relatively far from the first dielectric layer.
8. 8. The semiconductor device according to claim 3, wherein a dimension of the first gate contact portion in a thickness direction of the first semiconductor layer is smaller than a dimension of the first contact portion, the second contact portion, and the third contact portion in the thickness direction of the first semiconductor layer.
9. 9. The semiconductor device according to claim 2, further comprising a logic chip and a plurality of the first memory chips stacked on one side of the logic chip, wherein the first conductive structures of the plurality of the first memory chips are sequentially connected, the second conductive structures of the plurality of the first memory chips are sequentially connected, and the third conductive structures of the plurality of the first memory chips are sequentially connected, and the first conductive structure, the second conductive structure, and the third conductive structure of the first memory chip closest to the logic chip are all connected to the logic chip.
10. 10. The semiconductor device of claim 9, further comprising a second memory chip located on a side of the plurality of first memory chips that is relatively far from the logic chip, wherein the second memory chip comprises: A second transistor including a second active region in a second semiconductor layer and a second gate structure on a first side of the second semiconductor layer, the second gate structure being between the second semiconductor layer and the first memory chip; a fourth contact portion extending through the second dielectric layer covering the second transistor in a thickness direction of the second semiconductor layer and connected to a source of the second active region; a fifth contact portion extending through the second dielectric layer in a thickness direction of the second semiconductor layer and connected to a drain electrode of the second active region; the first conductive structure and the second conductive structure of the first memory chip farthest from the logic chip are respectively connected with the fourth contact portion and the fifth contact portion.
11. 11. The semiconductor device according to claim 10, wherein the second memory chip further comprises: And a second gate contact portion extending through the second dielectric layer in a thickness direction of the second semiconductor layer and connected to the second gate structure, wherein the second gate contact portion is connected to the conductive layer of the first memory chip farthest from the logic chip.
12. 12. The semiconductor device according to claim 10 or 11, wherein the first memory chip further comprises: a first dummy conductive structure extending through the first dielectric layer and the first semiconductor layer in a thickness direction of the first semiconductor layer; The second memory chip further includes: a second dummy conductive structure extending through the second dielectric layer and the second semiconductor layer in a thickness direction of the second semiconductor layer; A thermally conductive structure located on a second side of the second semiconductor layer and connected with the second dummy conductive structure; wherein a second side of the second semiconductor layer and a first side of the second semiconductor layer are opposite in a thickness direction of the second semiconductor layer; the first dummy conductive structures of the plurality of first memory chips are sequentially connected, the first dummy conductive structure of the first memory chip closest to the logic chip is connected with the logic chip, and the first dummy conductive structure of the first memory chip farthest from the logic chip is connected with the second dummy conductive structure.
13. 13. The semiconductor device of claim 12, wherein the first dummy conductive structure comprises a first dummy contact and a first dummy connection, wherein the first dummy contact and the first dummy connection extend through the first dielectric layer and the first semiconductor layer, respectively.
14. 14. The semiconductor device of claim 12, wherein the second dummy conductive structure comprises a second dummy contact and a second dummy connection, wherein the second dummy contact and the second dummy connection extend through the second dielectric layer and the second semiconductor layer, respectively, and wherein dimensions of the second dummy contact, the fourth contact, and the fifth contact in a thickness direction of the second semiconductor layer are substantially the same.
15. 15. The semiconductor device of claim 12, wherein the first memory chip comprises a plurality of the first dummy conductive structures; the second memory chip includes a plurality of the second dummy conductive structures; the first dummy conductive structures and the second dummy conductive structures are located in a first area of the semiconductor device, the first conductive structures, the second conductive structures and the third conductive structures are located in a second area of the semiconductor device, and the first area surrounds the second area.
16. 16. The semiconductor device of claim 12, further comprising a heat spreading structure on a side of the thermally conductive structure relatively remote from the second semiconductor layer.
17. 17. The semiconductor device according to claim 16, wherein the semiconductor device further comprises: The processing chip and the logic chip are arranged on one side of the substrate in parallel, wherein the heat dissipation structure covers the processing chip.
18. 18. The semiconductor device of claim 9, wherein the first memory chip further comprises a first bonding layer on a second side of the first semiconductor layer and a second bonding layer on a side of the first dielectric layer relatively far from the first semiconductor layer; The first bonding layer of one first memory chip of two adjacent first memory chips is bonded with the second bonding layer of the other first memory chip, the first bonding layer of the first memory chip closest to the logic chip is bonded with the logic chip, and the second bonding layer of the first memory chip farthest from the logic chip is bonded with the second memory chip.
19. 19. A method of fabricating a semiconductor device, comprising: The method comprises the steps of forming a first memory chip, wherein the first memory chip comprises a first transistor, a first conductive structure and a second conductive structure, the first transistor comprises a first active region located in a first semiconductor layer and a first grid structure located on the first side of the first semiconductor layer, the first conductive structure and the second conductive structure extend through the first semiconductor layer and a first dielectric layer covering the first transistor along the thickness direction of the first semiconductor layer, the first conductive structure is connected with a source electrode of the first active region, and the second conductive structure is connected with a drain electrode of the first active region.
20. 20. The method of manufacturing of claim 19, wherein forming the first memory chip comprises: Providing an initial first semiconductor layer; Forming the first transistor and the first dielectric layer on a first side of the initial first semiconductor layer; Forming a first contact, a second contact, a third contact, and a first gate contact extending through the first dielectric layer in a thickness direction of the initial first semiconductor layer such that the first contact connects a source of the first active region, the second contact connects a drain of the first active region, the third contact extends to a first side of the initial first semiconductor layer, and the first gate contact connects the first gate structure; Forming a conductive layer on one side of the first dielectric layer relatively far from the initial first semiconductor layer, wherein the conductive layer is respectively connected with the third contact part and the first gate contact part; And forming a first connection part, a second connection part and a third connection part which extend through the initial first semiconductor layer along the thickness direction of the initial first semiconductor layer on the second side of the initial first semiconductor layer, so that the first connection part is connected with the first contact part, the second connection part is connected with the second contact part, and the third connection part is connected with the third contact part, wherein the remaining initial first semiconductor layer forms the first semiconductor layer, the first connection part and the first contact part form the first conductive structure, the second connection part and the second contact part form the second conductive structure, and the third connection part and the third contact part form the third conductive structure.

Description

Semiconductor device and method for manufacturing the same Technical Field Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a semiconductor device and a method of fabricating the same. Background The high bandwidth memory (High Bandwidth Memory, HBM) can increase storage capacity, bandwidth, transmission speed, etc. by stacking multiple dynamic random access memory (Dynamic Random Access Memory, DRAM) chips using advanced packaging techniques (e.g., through silicon vias (Through Silicon Via, TSV), microbumps, etc.) and packaging with logic chips. In order to achieve electrical connection between adjacent DRAM chips, TSVs need to be formed in the DRAM. However, the depth and radial dimensions of TSVs in DRAM are large, which limits the data transmission of Input/Output (I/O) channels in HBMs. Disclosure of Invention In a first aspect of the disclosed embodiments, a semiconductor device is provided, including a first memory chip including: a first transistor including a first active region in a first semiconductor layer and a first gate structure on a first side of the first semiconductor layer; A first conductive structure extending through the first semiconductor layer and a first dielectric layer covering the first transistor in a thickness direction of the first semiconductor layer and connected with a source of the first active region; And a second conductive structure extending through the first dielectric layer and the first semiconductor layer in a thickness direction of the first semiconductor layer and connected with the drain electrode of the first active region. In some embodiments, the first memory chip further comprises: A first gate contact portion extending through the first dielectric layer in a thickness direction of the first semiconductor layer and connected to the first gate structure; And the third conductive structure extends through the first dielectric layer and the first semiconductor layer along the thickness direction of the first semiconductor layer, wherein the third conductive structure is connected with the first gate contact part through a conductive layer, and the conductive layer is positioned on one side of the first dielectric layer relatively far from the first semiconductor layer. In some embodiments, the first conductive structure includes a first contact and a first connection, wherein the first contact and the first connection extend through the first dielectric layer and the first semiconductor layer, respectively, the second conductive structure includes a second contact and a second connection, wherein the second contact and the second connection extend through the first dielectric layer and the first semiconductor layer, respectively, and the third conductive structure includes a third contact and a third connection, wherein the third contact and the third connection extend through the first dielectric layer and the first semiconductor layer, respectively. In some embodiments, the dimensions of the first contact, the second contact, and the third contact in the thickness direction of the first semiconductor layer are substantially the same. In some embodiments, the first, second, and third connection portions are substantially the same in size in a thickness direction of the first semiconductor layer. In some embodiments, the cross-sectional dimension of the first contact at a surface relatively closer to the first semiconductor layer is less than or equal to the cross-sectional dimension of the first contact at a surface relatively farther from the first semiconductor layer, the cross-sectional dimension of the second contact at a surface relatively closer to the first semiconductor layer is less than or equal to the cross-sectional dimension of the second contact at a surface relatively farther from the first semiconductor layer, and the cross-sectional dimension of the third contact at a surface relatively closer to the first semiconductor layer is less than or equal to the cross-sectional dimension of the third contact at a surface relatively farther from the first semiconductor layer. In some embodiments, the cross-sectional dimension of the first connection portion at a surface relatively close to the first dielectric layer is less than or equal to the cross-sectional dimension of the first connection portion at a surface relatively far from the first dielectric layer, the cross-sectional dimension of the second connection portion at a surface relatively close to the first dielectric layer is less than or equal to the cross-sectional dimension of the second connection portion at a surface relatively far from the first dielectric layer, and the cross-sectional dimension of the third connection portion at a surface relatively close to the first dielectric layer is less than or equal to the cross-sectional dimension of the third connection portion at a surface relatively far from the f