CN-121985532-A - Semiconductor structure, preparation method thereof, storage system and electronic equipment

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of bottleneck in the size miniaturization of the semiconductor structure. The semiconductor structure includes a capacitance structure and a plurality of first channel structures. The plurality of first channel structures are stacked along a first direction. The capacitor structure comprises a plurality of first electrode structures, a plurality of second electrode structures and a first dielectric layer, wherein the plurality of first electrode structures are stacked along a first direction, one first electrode structure is connected with one first channel structure, the second electrode structure comprises a first sub-portion and a plurality of second sub-portions, the plurality of second sub-portions and the plurality of first electrode structures are alternately stacked along the first direction, the first sub-portions are connected with the plurality of second sub-portions, and the first dielectric layer is located between the first electrode structure and the second electrode structure. Through the arrangement, an isolation layer is not required to be additionally arranged between the adjacent first electrode structures, and the semiconductor structure is beneficial to being miniaturized along the first direction.

Inventors

• OuYang Lujia
• YANG TAO
• DU XIAOLONG
• Ke Jiangang
• ZHOU WENXI

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260505

Application Date

20241025

Claims (18)

1. 1. A semiconductor structure, comprising: A plurality of first channel structures stacked in a first direction; The capacitor structure comprises a plurality of first electrode structures, a plurality of second electrode structures and a first dielectric layer, wherein the plurality of first electrode structures are stacked along the first direction, one first electrode structure is connected with one first channel structure, the second electrode structure comprises a first sub-portion and a plurality of second sub-portions, the plurality of second sub-portions and the plurality of first electrode structures are alternately stacked along the first direction, the plurality of second sub-portions are connected with the first sub-portions, and the first dielectric layer is positioned between the first electrode structures and the second electrode structures.
2. 2. The semiconductor structure of claim 1, wherein a dimension of the first channel structure in a first direction is the same as a dimension of the first electrode structure in the first direction.
3. 3. The semiconductor structure of claim 1, wherein the material of the first channel structure comprises indium gallium zinc oxide.
4. 4. The semiconductor structure of claim 3, wherein a dimension of the first channel structure in the first direction is less than 4nm.
5. 5. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes: The plurality of second channel structures are stacked along the first direction, the plurality of second channel structures and the plurality of first channel structures are arranged along a second direction, and the capacitor structure is positioned between the plurality of first channel structures and the plurality of second channel structures; the capacitor structure further includes: a plurality of third electrode structures stacked in the first direction, one of the third capacitor structures being connected to one of the second channel structures, the second electrode structure further including a plurality of third sub-portions stacked alternately with the plurality of third electrode structures in the first direction, the first sub-portion being connected to the plurality of third sub-portions; And the second dielectric layer is positioned between the first electrode structure and the third electrode structure.
6. 6. The semiconductor structure of claim 5, wherein the first sub-portion extends along a third direction and the first sub-portion extends through the plurality of first channel structures and the plurality of second channel structures along the first direction and the third direction, the third direction intersecting a plane in which the second direction and the first direction lie.
7. 7. The semiconductor structure of claim 5, wherein the first sub-portion, the plurality of second sub-portions, and the plurality of third sub-portions are integrally provided.
8. 8. The semiconductor structure of claim 5, wherein the semiconductor structure further comprises: A first gate layer extending along the first direction, the first gate layer being located on at least one side of the plurality of first channel structures along a third direction; The second grid electrode layer extends along the first direction and is positioned on at least one side of the plurality of second channel structures along the third direction, and the third direction intersects with a plane where the second direction and the first direction are positioned.
9. 9. The semiconductor structure of claim 8, wherein the first gate layer comprises a first sub-layer and a second sub-layer, the first sub-layer being located on one side of the plurality of first channel structures along the third direction, the second sub-layer being located on the other side of the plurality of first channel structures along the third direction.
10. 10. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises: A first bit line extending along the third direction and connected to an end of the first channel structure remote from the first electrode structure; and the second bit line extends along the third direction and is connected with one end of the second channel structure far away from the third electrode structure.
11. 11. The semiconductor structure of claim 5, wherein a plurality of said first channel structures are spaced apart along a third direction, a plurality of said first electrode structures are spaced apart along said third direction, a plurality of said first sub-portions are spaced apart along said third direction, said third direction intersecting a plane in which said second direction and said first direction lie; The semiconductor structure further comprises an isolation structure extending along the first direction, wherein the isolation structure is positioned between two adjacent first electrode structures along the third direction, and the isolation structure is also positioned between two adjacent second sub-parts along the third direction.
12. 12. A method of fabricating a semiconductor structure, comprising: Forming a capacitor structure, wherein the capacitor structure comprises a plurality of first electrode structures, a plurality of second electrode structures and a first dielectric layer, the plurality of first electrode structures are stacked along a first direction, the second electrode structures comprise a first sub-part and a plurality of second sub-parts, the plurality of second sub-parts and the plurality of first electrode structures are alternately stacked along the first direction, the first sub-parts are connected with the plurality of second sub-parts, and the first dielectric layer is positioned between the first electrode structures and the second electrode structures; A plurality of first channel structures are formed, the plurality of first channel structures are stacked along the first direction, and one of the first electrode structures is connected with one of the first channel structures.
13. 13. The method of fabricating a semiconductor structure of claim 12, further comprising, prior to said forming a capacitor structure: Forming a stacked structure including a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked in the first direction; forming a gate layer, wherein the gate layer penetrates through the stacked structure; And forming an isolation structure, wherein the isolation structure penetrates through the gate layer and the stacking structure, the gate layer positioned on one side of the isolation structure along the second direction is a first gate layer, the gate layer positioned on the other side of the isolation structure along the second direction is a second gate layer, and the second direction is intersected with the first direction.
14. 14. The method of manufacturing a semiconductor structure of claim 13, wherein forming a capacitor structure comprises: forming a groove, wherein the groove penetrates through the stacking structure and the isolation structure; Removing part of the dielectric layer through the groove to form a first filling space; forming a dielectric layer, wherein the dielectric layer covers part of the surface of the sacrificial layer, part of the surface of the dielectric layer and part of the surface of the isolation structure; filling electrode materials in the first filling space and the groove to form the second electrode structure; removing the sacrificial layer to form a second filling space; Electrode materials are filled in the second filling space, the electrode materials positioned on two sides of the first sub-portion along the first direction respectively form the first electrode structure and the third electrode structure, the dielectric layer positioned between the first electrode structure and the second electrode structure forms the first dielectric layer, and the dielectric layer positioned between the second electrode structure and the third electrode structure forms the second dielectric layer.
15. 15. The method of fabricating a semiconductor structure of claim 14, wherein forming a plurality of first channel structures comprises: filling semiconductor materials in the second filling space to form a plurality of first channel structures and a plurality of second channel structures, wherein the first channel structures are positioned at one end of the second electrode structures far away from the third electrode structures and are connected with the second electrode structures, the second channel structures are positioned at one end of the third electrode structures far away from the second electrode structures and are connected with the third electrode structures; And forming a first bit line and a second bit line, wherein the first bit line is positioned at one end of the first channel structure far away from the second electrode structure, the first bit line is connected with the first channel structure, the second bit line is positioned at one end of the second channel structure far away from the third electrode structure, and the second bit line is connected with the second channel structure.
16. 16. The method of claim 15, wherein the semiconductor material comprises indium gallium zinc oxide.
17. 17. A storage system, comprising: The semiconductor structure of any one of claims 1-11; a controller coupled to the semiconductor structure to control the semiconductor structure to store data.
18. 18. An electronic device comprising a motherboard and the memory system of claim 17, wherein the motherboard is electrically connected to the memory system.

Description

Semiconductor structure, preparation method thereof, storage system and electronic equipment Technical Field The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor structure, a preparation method thereof, a storage system and electronic equipment. Background With the continued evolution of dynamic random access memory (Dynamic Random Access Memory, DRAM), the memory density of planar DRAMs has gradually approached the process limit. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor structure, a method of manufacturing the same, a memory system, and an electronic device. The embodiment of the disclosure adopts the following technical scheme: In one aspect, a semiconductor structure is provided. Includes a capacitor structure and a plurality of first channel structures. The capacitor comprises a plurality of first channel structures, a plurality of second electrode structures and a first dielectric layer, wherein the plurality of first electrode structures and the second electrode structures are stacked along a first direction, one first electrode structure is connected with one first channel structure, the second electrode structure comprises a first sub-portion and a plurality of second sub-portions, the plurality of second sub-portions and the plurality of first electrode structures are stacked alternately along the first direction, the first sub-portions are connected with the plurality of second sub-portions, and the first dielectric layer is located between the first electrode structures and the second electrode structures. In some embodiments, the dimensions of the first channel structure in a first direction are the same as the dimensions of the first electrode structure in the first direction. In some embodiments, the material of the first channel structure comprises indium gallium zinc oxide. In some embodiments, the first channel structure has a dimension in the first direction of less than 4nm. In some embodiments, the semiconductor structure further includes a plurality of second channel structures stacked along the first direction, the plurality of second channel structures being arranged along a second direction with the plurality of first channel structures, the capacitor structure being located between the plurality of first channel structures and the plurality of second channel structures, the second direction intersecting the first direction, the capacitor structure further including a plurality of third electrode structures and a second dielectric layer. The plurality of third electrode structures are stacked along the first direction, one third capacitor structure is connected with one second channel structure, the second electrode structure further comprises a plurality of third sub-portions, the plurality of third sub-portions and the plurality of third electrode structures are stacked alternately along the first direction, the first sub-portion is connected with the plurality of third sub-portions, and the second dielectric layer is located between the first electrode structure and the third electrode structure. In some embodiments, the first sub-portion extends along a third direction, and the first sub-portion extends through the plurality of first channel structures and the plurality of second channel structures along the first direction and the third direction, the third direction intersecting a plane in which the second direction and the first direction lie. In some embodiments, the first sub-portion, the plurality of second sub-portions, and the plurality of third sub-portions are integrally provided. In some embodiments, the semiconductor structure further includes a first gate layer and a second gate layer, the first gate layer extending along the first direction and the first gate layer being located on at least one side of the plurality of first channel structures along a third direction, the second gate layer extending along the first direction and the second gate layer being located on at least one side of the plurality of second channel structures along the third direction, the third direction intersecting a plane in which the second direction and the first direction lie. In some embodiments, the first gate layer includes a first sub-layer located on one side of the plurality of first channel structures along the third direction and a second sub-layer located on the other side of the plurality of first channel structures along the third direction. In some embodiments, the semiconductor structure further includes a first bit line extending in the third direction and connected to an end of the first channel structure remote from the first electrode structure, and a second bit line extending in the third direction and connected to an end of the second channel structure remote from the third electrode structure. In some embodiments, the plurality of first channel structures are arra