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CN-121985533-A - Memory array, preparation method thereof, memory and electronic equipment

CN121985533ACN 121985533 ACN121985533 ACN 121985533ACN-121985533-A

Abstract

The embodiment of the application provides a memory array, a preparation method thereof, a memory and electronic equipment, and relates to the technical field of electronic equipment. The memory array includes a stacked structure, a multi-layered channel layer, and a transition structure. The stacked structure comprises a plurality of electrode layers which are stacked and arranged at intervals, the stacked structure is provided with a slot, the slot comprises an open hole and a plurality of sub-slots, the open hole penetrates through the plurality of electrode layers, the plurality of sub-slots are arranged on the wall of the open hole, and the sub-slots and the electrode layers are arranged on the same layer. The channel layer is disposed in the subslot. The transition structure is arranged in the subslot and on the surface of the channel layer, which is close to the electrode layer, and is respectively contacted with the channel layer and the electrode layer, the conductivity of the transition structure is greater than or equal to that of the channel layer, and the conduction band height of the transition structure material is greater than that of the electrode layer material. The embodiment of the application reduces the contact resistance between the electrode and the channel layer while not affecting the electric signal transmission capacity of the electrode.

Inventors

  • WANG YUQI
  • LU SHIHENG
  • ZHAO WANPENG
  • WU YING

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260505
Application Date
20241031

Claims (15)

  1. 1. A memory array, comprising: The stacked structure comprises a plurality of stacked electrode layers which are arranged at intervals, wherein the stacked structure is provided with a slot, the slot comprises an opening and a plurality of sub-slots, the opening penetrates through the plurality of electrode layers, the plurality of sub-slots are arranged on the wall of the opening, and the plurality of sub-slots are respectively arranged in the plurality of electrode layers; A plurality of sub-grooves formed in the substrate, each sub-groove having a plurality of grooves; the electrode layer and the channel layer are used for forming a transistor; The transition structure is arranged in the subslot, the transition structure is respectively contacted with the channel layer and the electrode layer, the conductivity of the material of the transition structure is greater than or equal to that of the material of the channel layer, and the conduction band height of the material of the transition structure is greater than that of the material of the electrode layer.
  2. 2. The memory array of claim 1, wherein the material of the transition structure is a conductor.
  3. 3. A memory array according to claim 1 or 2, wherein the material of the transition structure comprises a metal oxide.
  4. 4. A memory array according to any one of claims 1 to 3, wherein the transition structure comprises a plurality of sub-layers stacked along a direction in which the electrode layers point to the channel layer.
  5. 5. The memory array of claim 4, wherein the conduction band height of the multi-layered sub-layer material increases gradually along the direction in which the electrode layer points toward the channel layer.
  6. 6. The memory array of any one of claims 1-5, wherein the electrode layer comprises a plurality of conductive layers, the plurality of conductive layers are sequentially disposed around from inside to outside, and an outermost conductive layer is in contact with the transition structure.
  7. 7. The memory array of claim 6, wherein the plurality of conductive layers are oriented from an innermost conductive layer to an outermost conductive layer, the plurality of conductive layers having progressively higher conduction band heights.
  8. 8. The memory array of claim 6 or 7, wherein the material of the transition structure comprises InSnO, the electrode layer comprises a conductive layer of a metallic material and a conductive layer of InSnO material surrounding the conductive layer of metallic material, wherein the In content In the transition structure is lower than the In content In the electrode layer.
  9. 9. The memory array of any one of claims 1-8, wherein each of the channel layers comprises a plurality of channel layers spaced apart along a second direction, the plurality of channel layers corresponding to contact with the plurality of transition structures spaced apart; At least two transition structures corresponding to at least two channel layers in the same layer are in contact with the same electrode layer.
  10. 10. The memory array according to any one of claims 1 to 9, wherein the material of the transition structure is a partially or fully crystallized material.
  11. 11. The memory array of any of claims 1-10, wherein the material of the transition structure comprises one or more of InO, inGaO, inZnO, inSnO, znAlO, inSnZnO, inSnGaZnO.
  12. 12. A method of manufacturing a memory array, comprising: Forming a stacked structure, wherein the stacked structure comprises a plurality of electrode layers which are stacked and arranged at intervals; Forming a slot on the stacked structure, wherein the slot comprises an opening and a plurality of sub-slots, the opening penetrates through the multilayer electrode layer, the plurality of sub-slots are arranged on the wall of the opening, and the plurality of sub-slots are respectively arranged in the multilayer electrode layer; forming a transition structure on a part of the electrode layer, which belongs to the inner wall of the subslot, wherein the conduction band height of the transition structure material is larger than that of the electrode layer material; And forming a channel layer on the inner wall of the subslot, wherein the transition structure is respectively contacted with the channel layer and the electrode layer, and the conductivity of the material of the transition structure is greater than or equal to that of the material of the channel layer.
  13. 13. The method of manufacturing according to claim 12, wherein the forming of the transition structure on the portion of the electrode layer belonging to the inner wall of the sub-groove comprises: forming an amorphous buffer film on the inner wall of the slot; inducing partial crystallization of the amorphous buffer film on the electrode layer to form a transition structure; And removing the non-crystallized part of the amorphous buffer film.
  14. 14. A memory, comprising: the memory array of any one of claims 1-11; and the peripheral circuit is electrically connected with the storage array.
  15. 15. An electronic device, comprising: The memory of claim 14; and a bus electrically connected with the memory.

Description

Memory array, preparation method thereof, memory and electronic equipment Technical Field The present application relates to the field of electronic devices, and in particular, to a memory array, a method for manufacturing the memory array, a memory, and an electronic device. Background Memory, such as dynamic random access memory (dynamic random assess memory, DRAM), enables storage and reading of data. In order to meet the high-density memory demand, memories of three-dimensional stacked structures (e.g., 3D DRAM) are rapidly developed. However, compared with the conventional memory with a planar structure, the electrical performance of the memory with a three-dimensional stacked structure is reduced, for example, due to the large aspect ratio of the stacked structure, some doping processes and surface treatment processes commonly used in the planar structure are not applicable any more, so that the contact resistance between the channel layer and the electrode in the three-dimensional stacked structure cannot be effectively reduced, thereby affecting the electrical performance of the memory. Disclosure of Invention The embodiment of the application provides a memory array, a preparation method thereof, a memory and electronic equipment, and aims to reduce the contact resistance between an electrode and a channel layer while not affecting the electric signal transmission capacity (conductivity) of the electrode (source electrode and drain electrode) per se, thereby improving the transmission capacity between the electrode and the channel layer and optimizing the electrical performance of the memory array. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: In a first aspect, a memory array is provided that includes a stacked structure, a multi-layered channel layer, and a transition structure. The stacked structure comprises a plurality of stacked electrode layers which are arranged at intervals, the stacked structure is provided with a slot, the slot comprises an open hole and a plurality of sub-slots, the open hole penetrates through the plurality of electrode layers, the plurality of sub-slots are arranged on the wall of the open hole, and the plurality of sub-slots are respectively arranged in the plurality of electrode layers. The electrode layer and the channel layer are used for forming a transistor. The transition structure is arranged in the subslot, the transition structure is respectively contacted with the channel layer and the electrode layer, the conductivity of the material of the transition structure is larger than that of the material of the channel layer, and the conduction band height of the material of the transition structure is larger than that of the material of the electrode layer. In the memory array provided by the embodiment of the application, the transition structure is arranged, the conduction band height of the transition structure is higher than that of the electrode layer, and the conductivity is higher than that of the channel layer, so that the electron transmission capability between the transition structure and the electrode layer is higher than that between the electrode layer and the channel layer when the electrode layer is directly contacted with the channel layer, and the potential barrier height between the transition structure and the channel layer is lower than that between the electrode layer and the channel layer when the electrode layer is directly contacted with the channel layer, thereby improving the overall transmission capability of the electrode layer connected with the channel layer through the transition structure, optimizing the electrical performance of the memory array, for example, because the transmission capability between the electrode layer and the channel layer is enhanced, under the same driving voltage, the memory array provided by the embodiment of the application can have larger driving current, so that the charging speed of a capacitor in the memory array is increased, or for example, under the condition that the access speed requirement of the memory array is satisfied (namely, the driving current is unchanged), the overall power consumption of the memory array can be reduced only by loading a lower voltage on a transistor, and the whole power consumption of the memory array can be realized. In addition, the transition structure is arranged in the sub-groove, namely only on the part of the electrode layer opposite to the channel layer (namely the part of the electrode layer exposed by the sub-groove), so that the resistance of the electrode layer is not greatly increased, namely, the storage array provided by the embodiment of the application can improve the carrier transmission capability between the electrode layer and the channel layer while the signal transmission capability of the electrode layer (such as the transmission capability of an electric signal transmitt