CN-121985534-A - Memory device, electronic apparatus, and method of manufacturing memory device

Abstract

Embodiments of the present disclosure provide a memory device, an electronic apparatus, and a method of manufacturing the memory device. The memory device includes a first word line, a first bit line, an extension direction of the first word line intersecting an extension direction of the first bit line, a first charge storage element, and a first transistor. The first transistor includes a first active region including a first region electrically coupled to the first charge storage element, a second region electrically coupled to the first bit line, and a first channel region located between the first region and the second region, the first channel region and the second region being disposed along an extending direction of the first word line, and a first gate electrically coupled to the first word line, the extending direction of the first gate being the same as the extending direction of the first word line, the first gate further extending in a direction intersecting both the extending direction of the first word line and the extending direction of the first bit line, and facing the first channel region.

Inventors

• WANG HENG
• LU SHIHENG
• WU YING
• ZHAO WANPENG
• LIU CHANGZE

Assignees

• 华为技术有限公司

Dates

Publication Date

20260505

Application Date

20260202

Claims (17)

1. 1. A memory device, comprising: A first word line; A first bit line, an extension direction of the first word line intersecting an extension direction of the first bit line; a first charge storage element, and A first transistor, comprising: a first active region including a first region electrically coupled to the first charge storage element, a second region electrically coupled to the first bit line, and a first channel region between the first region and the second region, the first channel region, and the second region being disposed along an extension direction of the first word line, an A first gate electrically coupled to the first word line, the first gate extending in the same direction as the first word line, the first gate further extending in a direction intersecting both the first word line and the first bit line and facing the first channel region.
2. 2. The memory device of claim 1, further comprising: A first contact conductive layer coupled between the first charge storage element and the first region, the first contact conductive layer extending in the same direction as the first word line, the first contact conductive layer also extending in a direction intersecting both the first word line and the first bit line and contacting the first region, and/or And a second contact conductive layer coupled between the first bit line and the second region, the second contact conductive layer extending in the same direction as the first word line, the second contact conductive layer further extending in a direction intersecting both the first word line and the first bit line, and contacting the second region.
3. 3. The memory device according to claim 1 or 2, further comprising a second transistor adjacent to the first transistor in an extending direction of the first bit line, the first active region of the first transistor being disconnected from an active region of the second transistor.
4. 4. The memory device of claim 2, further comprising a convex portion extending in the same direction as the first bit line, the convex portion including a first outer side, a top surface, and a second outer side, the first gate and the first active region being stacked over and surrounding the convex portion, The first channel region extends along the first outer side surface, the top surface and the second outer side surface and faces the first gate, The first contact conductive layer is disposed along the extending directions of the first outer side face, the top face and the second outer side face and contacts the first area, and/or the second contact conductive layer is disposed along the extending directions of the first outer side face, the top face and the second outer side face and contacts the second area.
5. 5. The memory device of claim 4, wherein the first contact conductive layer does not contact the first region over a first portion of the surface of the first outer side and over a second portion of the surface of the second outer side, and/or the second contact conductive layer does not contact the second region over a third portion of the surface of the first outer side and over a fourth portion of the surface of the second outer side, The first, second, third and fourth partial surfaces include surfaces of the first and second outer sides proximate the bottom of the male portion.
6. 6. The memory device of claim 5, wherein the memory device further comprises a third transistor adjacent to the first transistor along the direction of extension of the first bit line, the first active region of the first transistor being connected to an active region of the third transistor.
7. 7. The memory device of claim 4, wherein the male portion comprises at least one of a metal and silicon, In the case where the convex portion includes a metal material, the first gate is the convex portion.
8. 8. The memory device of claim 2, further comprising a first concave portion extending in the same direction as the first word line, the first concave portion including a first inner side surface, a first bottom surface, and a second inner side surface, the first gate and the first active region being disposed over and overlying the first concave portion, The first channel region extends along the first inner side surface, the first bottom surface and the second inner side surface and faces the first gate, The first contact conductive layer is filled inside the first concave portion and disposed along the extending directions of the first inner side surface, the first bottom surface, and the second inner side surface and contacts the first region, and/or the second contact conductive layer is filled inside the first concave portion and disposed along the extending directions of the first inner side surface, the first bottom surface, and the second inner side surface and contacts the second region.
9. 9. The memory device of claim 1, further comprising a second concave portion extending in the same direction as the first word line, the second concave portion including a third inner side surface, a second bottom surface, and a fourth inner side surface, the first gate electrode and the first active region being stacked on and covering the second concave portion, the first active region further being filled at least inside the second concave portion, The first channel region extends along the third inner side, the second bottom surface, and the fourth inner side and faces the first gate.
10. 10. The memory device of claim 1 or 2, further comprising: A second word line extending parallel to the first word line; A second charge storage element; a fourth transistor comprising: A second active region including a third region electrically coupled to the second charge storage element, a fourth region electrically coupled to the first bit line, and a second channel region between the third region and the fourth region, the second channel region, and the third region being disposed along an extension direction of the second word line, and And a second gate electrode electrically coupled to the second word line, the second gate electrode extending in the same direction as the second word line, the second gate electrode further extending in a direction intersecting both the second word line and the first bit line and facing the second channel region.
11. 11. The memory device of claim 10, wherein the first gate is aligned with the second gate in the direction of extension of the second word line, The second region is connected to the fourth region in an extending direction of the second word line or an extending direction of the first bit line, or the second region and the fourth region are the same region.
12. 12. The memory device of claim 1 or 2, wherein the first bit line and the first charge storage element are located on a first side of the first active region in a plane perpendicular to an extension direction of the first word line, and the first gate and the first word line are located on a second side of the first active region in a plane perpendicular to the extension direction of the first word line, the second side being opposite the first side.
13. 13. The memory device of claim 2, wherein the memory device further comprises a first via and a second via, the first via contacting the first charge storage element and the first contact conductive layer, the second via contacting the first bit line and the second contact conductive layer.
14. 14. The memory device of claim 1, wherein the first transistor further comprises a dielectric layer between the first active region and the first gate, the dielectric layer extending along the first gate in a plane perpendicular to a direction of extension of the first word line.
15. 15. The memory device of claim 1 or 2, wherein the first active region comprises an oxide semiconductor material.
16. 16. An electronic device, comprising: power supply device, and The memory device of any one of claims 1 to 15.
17. 17. A method of manufacturing a memory device, comprising: Forming a word line; Forming a convex portion or a concave portion over the word line; forming a gate and an active region on a top surface and two outer side surfaces of the convex portion, or forming a gate and an active region on a bottom surface and two inner side surfaces of the concave portion; forming a first contact conductive layer on a first region of the active region; Forming a second contact conductive layer on a second region of the active region; Forming a second via and a bit line, the second via being coupled between the bit line and the second contact conductive layer, and A first via and a charge storage element are formed, the first via being coupled between the charge storage element and the first contact conductive layer.

Description

Memory device, electronic apparatus, and method of manufacturing memory device Technical Field The present disclosure relates generally to the field of semiconductors, and more particularly, to a memory device, an electronic apparatus, and a method of manufacturing the memory device. Background The memory is a core component of modern electronic devices (such as computers, smart phones, data center servers, and internet of things devices) and has the function of storing program instructions and data. With the rapid development of artificial intelligence, big data, cloud computing and other technologies, unprecedented higher requirements are placed on the performance (including storage density, read-write speed, power consumption and reliability) of memories. For example, in logic, memory chip applications, high density integration of transistors is a key to improving chip performance and capacity, and integrating different logic, memory, and other functional units in a vertical direction is a trend in future integrated circuit technology. Currently, schemes are proposed to improve device performance such as integration density. However, these schemes may cause degradation of performance in other aspects while improving the integration density, and cannot meet the development requirements of semiconductor technology. Disclosure of Invention In order to solve the above-described problems, embodiments of the present disclosure provide a memory device, an electronic apparatus, and a method of manufacturing the memory device. In a first aspect of the present disclosure, there is provided a memory device including a first word line, a first bit line, an extension direction of the first word line intersecting an extension direction of the first bit line, a first charge storage element, and a first transistor including a first active region including a first region electrically coupled to the first charge storage element, a second region electrically coupled to the first bit line, and a first channel region located between the first region and the second region, the first channel region and the second region being disposed along the extension direction of the first word line, and a first gate electrically coupled to the first word line, the extension direction of the first gate being the same as the extension direction of the first word line, the first gate further extending in a direction intersecting both the extension direction of the first word line and the extension direction of the first bit line, and facing the first channel region. According to the embodiment of the disclosure, the grid electrodes extend in two different directions, so that a three-dimensional structure is formed, and the channel width of the memory device can be obviously increased on the premise of not increasing the occupied area of the memory device, so that the driving current is improved to maintain the high-speed reading and writing performance of the circuit. In addition, by making the memory device current direction coincide with the word line extending direction, the process steps can be simplified, and further improvement of the driving capability can be facilitated. In some embodiments of the present disclosure, the memory device further includes a first contact conductive layer coupled between the first charge storage element and the first region, the first contact conductive layer extending in a direction that intersects both the extending direction of the first word line and the extending direction of the first bit line and contacting the first region, and/or a second contact conductive layer coupled between the first bit line and the second region, the second contact conductive layer extending in a direction that intersects both the extending direction of the first word line and the extending direction of the first bit line and contacting the second region. By this embodiment, the contact size of the contact conductive layer with the active region is increased, so that the contact resistance can be reduced and the current passing through can be increased. In addition, the grid electrode and the source/drain region are overlapped, so that the doping of the contact region is improved, and the current limiting effect caused by contact is remarkably relieved. In some embodiments of the present disclosure, the memory device further includes a second transistor adjacent to the first transistor along an extension direction of the first bit line, the first active region of the first transistor being disconnected from the active region of the second transistor. By this embodiment, by turning off the active regions of the adjacent transistors, leakage current between the adjacent memory cells can be prevented, so that the distance between the adjacent transistors can be further compressed and the memory density can be increased. In some embodiments of the present disclosure, the memory device further includes a convex portion having a