CN-121985535-A - Method for forming semiconductor structure

Abstract

A method of forming a semiconductor structure is provided. The method comprises the following steps. A bit line structure is formed on a substrate. A spacer structure is formed on sidewalls of the bit line structure. A conductive layer is formed to cover the bit line structure and the spacer structure. A mask is formed to cover the conductive layer. The mask is planarized to expose the conductive layer. The conductive layer is recessed to form a contact plug. This approach can avoid loss of the outermost thickness of the spacer structure.

Inventors

• SHI YITING
• LIN YUTING

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260505

Application Date

20260205

Priority Date

20251015

Claims (20)

1. 1. A method of forming a semiconductor structure, the method comprising: Forming a bit line structure on a substrate; forming a spacer structure on a sidewall of the bit line structure; forming a conductive layer to cover the bit line structure and the spacer structure; forming a mask to cover the conductive layer; Planarizing the mask to expose the conductive layer, and The conductive layer is recessed to form a contact plug.
2. 2. The method of claim 1, wherein a top surface of the conductive layer is flush with a top surface of the bit line structure after forming the conductive layer overlying the bit line structure and the spacer structure.
3. 3. The method of claim 1, wherein the spacer structure comprises a first spacer layer, a second spacer layer, and a third spacer layer sequentially formed on the sidewalls of the bit line structure.
4. 4. The method of claim 1, wherein forming the conductive layer overlying the bit line structure and the spacer structure comprises: Depositing the conductive layer over the bit line structures and the spacer structures such that a top surface of the conductive layer is higher than a top surface of the bit line structures, and Planarizing the conductive layer.
5. 5. The method of claim 4, wherein the spacer structure is completely covered by the conductive layer after planarizing the conductive layer.
6. 6. The method of claim 1, wherein a top surface of the contact plug is lower than a top surface of a conductive layer of the bit line structure after recessing the conductive layer to form the contact plug.
7. 7. The method of claim 1, further comprising: and forming a cobalt silicide layer on the contact plug.
8. 8. The method of claim 1, wherein the spacer structure comprises a first spacer layer, a second spacer layer, and a third spacer layer sequentially formed on the sidewalls of the bit line structure, and the method further comprises: removing the second spacer layer after recessing the conductive layer to form the contact plug, and And forming a cobalt silicide layer on the contact plug.
9. 9. A method of forming a semiconductor structure, the method comprising: Forming a peripheral structure on a peripheral region of a substrate, and forming an intermediate structure on an array region of the substrate, wherein the intermediate structure comprises a bit line structure, a spacer structure and a conductive layer, the spacer structure covers the bit line structure, and the conductive layer covers the bit line structure and the spacer structure; forming a mask covering the intermediate structure and the peripheral structure; Planarizing the mask to expose the conductive layer of the intermediate structure, and The conductive layer is recessed to form a contact plug.
10. 10. The method of claim 9, wherein the intermediate structure comprises a top surface of the conductive layer being flush with a top surface of the bit line structure.
11. 11. The method of claim 9, wherein forming the intermediate structure on the array region of the substrate comprises: Forming the spacer structure on the sidewall of the bit line structure, wherein the spacer structure comprises a first spacer layer, a second spacer layer and a third spacer layer, and the second spacer layer is arranged between the first spacer layer and the third spacer layer; Depositing the conductive layer over the bit line structures and the spacer structures such that a top surface of the conductive layer is higher than a top surface of the bit line structures, and Planarizing the conductive layer.
12. 12. The method of claim 11, wherein the spacer structure is completely covered by the conductive layer after planarizing the conductive layer.
13. 13. The method of claim 9, wherein a top surface of the contact plug is lower than a top surface of a conductive layer of the bit line structure after recessing the conductive layer to form the contact plug.
14. 14. The method of claim 9, wherein forming the peripheral structure on the peripheral region of the substrate comprises: forming a plurality of transistors on the substrate; forming a dielectric layer to cover the transistors, and A plurality of openings are formed in the dielectric layer and between the plurality of transistors.
15. 15. The method of claim 14, wherein the plurality of transistors comprises a dummy transistor, a first type transistor, and a second type transistor, and the first type transistor is different than the second type transistor.
16. 16. The method of claim 15, wherein forming the mask to cover the intermediate structure and the peripheral structure comprises: The plurality of openings are filled with the mask.
17. 17. The method of claim 16, further comprising: The mask is planarized to expose top surfaces of the dummy transistors, the first type transistors, and the second type transistors.
18. 18. The method of claim 17, further comprising: removing the mask within the plurality of openings, and And forming a cobalt silicide layer in the openings.
19. 19. The method of claim 9, further comprising: and forming a cobalt silicide layer on the contact plug.
20. 20. The method of claim 9, wherein the spacer structure comprises a first spacer layer, a second spacer layer, and a third spacer layer sequentially formed on sidewalls of the bit line structure, and the method further comprises: removing the second spacer layer after recessing the conductive layer to form the contact plug, and And forming a cobalt silicide layer on the contact plug.

Description

Method for forming semiconductor structure Technical Field The present invention relates to a method of forming a semiconductor structure. More particularly, the present invention relates to a method of forming a dynamic random access memory (dynamic random access memory, DRAM) structure having an air gap. Background With the rapid development of the electronics industry, integrated circuits (INTEGRATED CIRCUIT, ICs) have achieved high performance and miniaturization. Technological advances in materials and design of integrated circuits continue to produce new generations of integrated circuits, each of which is smaller and more complex than the previous generation. A dynamic random access memory (dynamic random access memory, DRAM) element is a random access memory that stores each bit of metadata in a separate capacitor within an integrated circuit. Typically, DRAMs are arranged in square arrays with one capacitor and transistor per cell. Currently, vertical transistors for 4F 2 DRAM memory cells have been developed, where F represents the photolithographic minimum feature width or critical dimension (critical dimension, CD). However, as the word line pitch is reduced, DRAM manufacturers face a significant challenge in reducing the area of memory cells. The above description of "background art" merely provides background art, and it is not admitted that the above description of "background art" reveals the subject matter of the present invention, do not constitute background art to the present invention, and any description of "background art" above should not be taken as part of any of the present invention. Disclosure of Invention An aspect of the present invention is to provide a method of forming a semiconductor. The method comprises the following steps. A bit line structure is formed on a substrate. A spacer structure is formed on sidewalls of the bit line structure. A conductive layer is formed to cover the bit line structure and the spacer structure. A mask is formed to cover the conductive layer. The mask is planarized to expose the conductive layer. The conductive layer is recessed to form a contact plug. In some embodiments, after forming the conductive layer overlying the bit line structures and the spacer structures, a top surface of the conductive layer is flush with a top surface of the bit line structures. In some embodiments, the spacer structure includes a first spacer layer, a second spacer layer, and a third spacer layer sequentially formed on sidewalls of the bit line structure. In some embodiments, forming the conductive layer overlying the bit line structures and the spacer structures includes depositing the conductive layer over the bit line structures and the spacer structures such that a top surface of the conductive layer is above a top surface of the bit line structures, and planarizing the conductive layer. In some embodiments, after planarizing the conductive layer, the spacer structure is completely covered by the conductive layer. In some embodiments, after recessing the conductive layer to form a contact plug, a top surface of the contact plug is lower than a top surface of the conductive layer of the bit line structure. In some embodiments, the method of forming a semiconductor structure further includes forming a cobalt silicide layer on the contact plug. In some embodiments, the spacer structure includes a first spacer layer, a second spacer layer, and a third spacer layer sequentially formed on sidewalls of the bit line structure, and the method further includes removing the second spacer layer after recessing the conductive layer to form a contact plug, and forming a cobalt silicide layer on the contact plug. Another aspect of the present invention is to provide a method of forming a semiconductor. The method comprises the following steps. Forming a peripheral structure on the peripheral region of the substrate, and forming an intermediate structure on the array region of the substrate, wherein the intermediate structure comprises a bit line structure, a spacer structure and a conductive layer, the spacer structure covers the bit line structure, and the conductive layer covers the bit line structure and the spacer structure. A mask is formed to cover the intermediate structure and the peripheral structure. The mask is planarized to expose the conductive layer of the intermediate structure. The conductive layer is recessed to form a contact plug. In some embodiments, the intermediate structure includes a top surface of the conductive layer being flush with a top surface of the bit line structure. In some embodiments, forming the intermediate structure on the array region of the substrate includes forming a spacer structure on sidewalls of the bit line structure, wherein the spacer structure includes a first spacer layer, a second spacer layer, and a third spacer layer, and the second spacer layer is disposed between the first spacer layer and the third spacer layer, dep