CN-121985536-A - Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device includes a first polysilicon layer and a second polysilicon layer. The first polysilicon layer has a high phosphorus to silicon (P/S) ratio of between 1 and 1.5 and is disposed in at least one trench of the substrate. A second polysilicon layer having a low P/S ratio of between 0.01 and 0.09 is in contact with the first polysilicon layer and disposed in the trench. The semiconductor memory device and the manufacturing method thereof of the invention propose a configuration mode with high and low P/S ratio, when the first and second polysilicon layers of bit line contact are deposited in the bit line trench, the intermediate P/S ratio is not used, so as to reduce hole defects and maintain electrical performance.

Inventors

• ZHANG JINGJIE
• JI CHENGYAN

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260505

Application Date

20260210

Priority Date

20251130

Claims (18)

1. 1. A method of manufacturing a semiconductor memory device, comprising: forming at least one groove on a substrate; Forming a first polysilicon layer in the trench, the first polysilicon layer having a high phosphorus to silicon (P/S) ratio of 1 to 1.5, and A second polysilicon layer is formed in contact with the first polysilicon layer and in the trench, the second polysilicon layer having a low P/S ratio of between 0.01 and 0.09.
2. 2. The method as recited in claim 1, further comprising: forming a buffer polysilicon layer over the second polysilicon layer, the buffer polysilicon layer having a P/S ratio of less than 0.01, wherein the buffer polysilicon layer is over the trench.
3. 3. The method of claim 1, wherein the low P/S ratio of the second polysilicon layer is equal to 0.03.
4. 4. The method of claim 1, wherein the low P/S ratio of the second polysilicon layer is equal to 0.04.
5. 5. The method of claim 2, wherein the P/S ratio of the buffered polysilicon layer is equal to zero.
6. 6. The method of claim 1, wherein the first polysilicon layer has a conformal thickness equal to 9 nanometers.
7. 7. The method of claim 1, wherein the first polysilicon layer has a conformal thickness equal to 5 nanometers.
8. 8. The method of claim 7, wherein the second polysilicon layer has an average thickness equal to 25 nanometers.
9. 9. The method of claim 1, wherein the first polysilicon layer and the second polysilicon layer have an average aggregate thickness equal to 30 nanometers.
10. 10. A semiconductor memory device, comprising: a first polysilicon layer having a high phosphorus to silicon (P/S) ratio of 1 to 1.5 and disposed in at least one trench of the substrate, and And a second polysilicon layer having a low P/S ratio of 0.01 to 0.09, in contact with the first polysilicon layer and disposed in the trench.
11. 11. The semiconductor memory device according to claim 10, further comprising: and the buffer polysilicon layer is provided with a P/S ratio smaller than 0.01 and is arranged on the second polysilicon layer, wherein the buffer polysilicon layer is positioned on the groove.
12. 12. The semiconductor memory device of claim 11, wherein the P/S ratio of the buffer polysilicon layer is equal to zero.
13. 13. The semiconductor memory device according to claim 11, wherein the buffer polysilicon layer has an average thickness equal to 40 nanometers.
14. 14. The semiconductor memory device according to claim 10, wherein the low P/S ratio of the second polysilicon layer is equal to 0.03.
15. 15. The semiconductor memory device according to claim 10, wherein the low P/S ratio of the second polysilicon layer is equal to 0.04.
16. 16. The semiconductor memory device of claim 10, wherein the first polysilicon layer has a conformal thickness equal to 9 nanometers.
17. 17. The semiconductor memory device according to claim 15, wherein the second polysilicon layer has an average thickness equal to 25 nanometers.
18. 18. The semiconductor memory device according to claim 10, wherein the first polysilicon layer and the second polysilicon layer have an average total thickness equal to 30 nanometers.

Description

Semiconductor memory device and method for manufacturing the same Technical Field The invention relates to a semiconductor memory device and a method for manufacturing the same. Background Integrated circuit devices, also known as semiconductor chips, may include millions of transistors and other circuit elements fabricated on a single silicon crystal substrate (wafer). In order to increase the performance of integrated circuit devices and reduce the manufacturing costs, there is a continual effort in the Dynamic Random Access Memory (DRAM) industry to reduce the device size. In the DRAM industry, it is a challenge to develop high quality bit lines with low resistance and low leakage. To reduce resistance in the bit line process, it has been developed to deposit highly PH3 doped polysilicon in the bit line contact holes. However, higher concentrations of PH3 doping more easily increase void (void) defects, which in turn lead to side effects of tungsten (W) extrusion. Disclosure of Invention The present invention provides an innovative semiconductor memory device and a method for fabricating the same, which solve the problems of the prior art. In some embodiments of the present invention, a method of fabricating a semiconductor memory device includes forming at least one trench on a substrate, forming a first polysilicon layer in the trench, the first polysilicon layer having a high phosphorus to silicon (P/S) ratio of between 1 and 1.5, and forming a second polysilicon layer in contact with the first polysilicon layer and in the trench, the second polysilicon layer having a low P/S ratio of between 0.01 and 0.09. In some embodiments of the present invention, the method further comprises forming a buffered polysilicon layer over the second polysilicon layer, the buffered polysilicon layer having a P/S ratio of less than 0.01, wherein the buffered polysilicon layer is located over the trench. In some embodiments of the invention, the low P/S ratio of the second polysilicon layer is equal to 0.03. In some embodiments of the invention, the low P/S ratio of the second polysilicon layer is equal to 0.04. In some embodiments of the present invention, the P/S ratio of the buffered polysilicon layer is equal to zero. In some embodiments of the invention, the first polysilicon layer has a conformal thickness equal to 9 nanometers. In some embodiments of the invention, the first polysilicon layer has a conformal thickness equal to 5 nanometers. In some embodiments of the invention, the second polysilicon layer has an average thickness equal to 25 nanometers. In some embodiments of the invention, the first polysilicon layer and the second polysilicon layer have an average combined thickness equal to 30 nanometers. In some embodiments of the invention, a semiconductor memory device includes a first polysilicon layer having a high P/S ratio of 1 to 1.5 and disposed in at least one trench of a substrate, and a second polysilicon layer having a low P/S ratio of 0.01 to 0.09 and disposed in the trench in contact with the first polysilicon layer. In some embodiments of the present invention, the semiconductor memory device further includes a buffer polysilicon layer having a P/S ratio of less than 0.01 disposed over the second polysilicon layer, wherein the buffer polysilicon layer is disposed over the trench. In some embodiments of the present invention, the P/S ratio of the buffered polysilicon layer is equal to zero. In some embodiments of the invention, the buffered polysilicon layer has an average thickness equal to 40 nanometers. In some embodiments of the invention, the low P/S ratio of the second polysilicon layer is equal to 0.03. In some embodiments of the invention, the low P/S ratio of the second polysilicon layer is equal to 0.04. In some embodiments of the invention, the first polysilicon layer has a conformal thickness equal to 9 nanometers. In some embodiments of the invention, the second polysilicon layer has an average thickness equal to 25 nanometers. In some embodiments of the invention, the first polysilicon layer and the second polysilicon layer have an average combined thickness equal to 30 nanometers. In view of the above, the semiconductor memory device and the method for fabricating the same of the present invention provide a high/low P/S ratio configuration, in which the first and second polysilicon layers of bit line contacts are deposited in the bit line trenches without using an intermediate P/S ratio, thereby reducing hole defects and maintaining electrical performance. The following description will make detailed description of the above description in terms of embodiments, and provide further explanation of the technical solution of the present invention. Drawings The foregoing and other objects, features, advantages and embodiments of the invention will be apparent from the following description taken in conjunction with the accompanying drawings in which: FIG. 1 is a cross-sectional view il