CN-121985537-A - Semiconductor device and manufacturing method thereof

CN121985537ACN 121985537 ACN121985537 ACN 121985537ACN-121985537-A

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a substrate, an active column body vertically arranged, a gate dielectric layer, a gate electrode, a drain electrode expansion liner layer and a grid supporting structure. The grid support structure is formed on the outer side of the drain extension liner layer, comprises at least two material layers and is in a ladder-shaped structure along the direction of a word line. The method of manufacturing includes the steps of forming an active pillar pattern, forming a gate dielectric layer only in a channel region, forming a drain extension liner layer, and forming the multi-layered ladder-grid support structure by a self-aligned process. The invention obviously enhances the mechanical stability of the column body, reduces parasitic capacitance and leakage current and comprehensively improves the performance and reliability of the device through the unique structural design and the self-aligned manufacturing process while effectively reducing the contact resistance of the drain electrode.

Inventors

Jin Zaiyou
Jin Rongkuan
LI HUIEN
QI BIAO
SHI HAORAN
SHAO DALI

Assignees

杭州星原驰半导体有限公司

Dates

Publication Date: 20260505
Application Date: 20260330

Claims (10)

1. A semiconductor device, comprising: A substrate (1); An active column (2) vertically arranged on the substrate (1), wherein a plurality of active columns (2) are arranged, and each active column (2) comprises a source electrode region (21), a channel region (22) and a drain electrode region (23); Characterized by further comprising: A gate dielectric layer (3) formed in a channel region (22) of the active column (2); the grid electrode (4) is arranged around the grid dielectric layer (3); A drain extension liner layer (5) formed on the sidewalls of the drain region (23) of the active pillars (2); -a grid support structure (6) formed outside the drain extension spacer layer (5), the grid support structure (6) comprising a plurality of material layers; There is a first oxide layer located between the drain extension spacer layer (5) and the grid support structure (6).
2. The semiconductor device according to claim 1, wherein the material of the grid support structure (6) comprises a silicon nitride based material selected from at least one of silicon nitride, silicon carbide nitride, boron nitride silicon or silicon carbonitride; And/or the number of the groups of groups, Along the word line direction, the grid support structure (6) is of a ladder-shaped structure.
3. The semiconductor device according to claim 1, characterized in that the grid support structure (6) is in direct contact with the metal material of the gate (4) in the depth direction or an oxide spacer layer is provided between the grid support structure (6) and the metal material of the gate (4).
4. The semiconductor device according to claim 1, characterized in that the thickness of the oxide layer is smaller than the thickness of the gate dielectric layer (3).
5. The semiconductor device of claim 1, further comprising a bit line isolation structure extending in a bit line direction and a word line isolation structure extending in a word line direction; Wherein, the The material of the word line isolation structure is the same as that of the grid support structure (6) or belongs to the same kind of silicon nitride series material.
6. A semiconductor device according to claim 1, characterized in that the drain extension spacer layer (5) is a silicon layer formed by selective epitaxial growth or chemical vapor deposition.
7. A method of manufacturing a semiconductor device, comprising the steps of: Providing a substrate, and forming an active column pattern on the substrate; forming a gate dielectric layer in the channel region of the active column; forming a drain extension liner layer on the side wall of the drain region of the active column by selective epitaxial growth or chemical vapor deposition; And forming a grid support structure which is provided with a plurality of dielectric material layers and is in a ladder-shaped structure along the word line direction outside the drain extension liner layer through a self-alignment process.
8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the active pillar pattern, comprising: sequentially forming a silicon germanium layer and a silicon layer on the substrate; etching the silicon layer along the bit line direction by taking the silicon germanium layer as an etching stop layer to form a first gap; and after filling the first gap, etching along a word line direction perpendicular to the bit line direction to form a second gap, wherein the bottom depth of the second gap is smaller than that of the first gap.
9. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the ladder grid support structure, comprising: Oxidizing the surface of the drain electrode extension liner layer to form a first oxide layer; Depositing a silicon nitride based material layer on the first oxide layer; etching back the silicon nitride material layer to define a ladder-shaped structure; Wherein the thickness of the first oxide layer is less than a thickness that can be removed by a subsequent oxide etch back process to expose the channel region such that the first oxide layer remains under the grid support structure.
10. The method for manufacturing a semiconductor device according to claim 7, characterized in that the method for manufacturing further comprises the steps of: And forming a grid electrode surrounding the grid dielectric layer, wherein the side wall of the grid electrode is in direct contact with the grid supporting structure in the depth direction, or an oxide spacing layer is formed between the grid electrode and the grid supporting structure.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor device manufacturing methods, and more particularly, to a semiconductor device and a method for manufacturing the same. Background With the development of semiconductor memory devices (e.g., dynamic random access memory, DRAM) toward higher integration and smaller cell sizes, the 4F2 pillar transistor technology has become one of the key paths for achieving high density memory because it can achieve one memory cell within four times the square of a single minimum feature size (F). In this technique, a vertical silicon pillar (Pillar) serves as the channel of the transistor, with its top region constituting the drain. However, as feature size (DR) is reduced, the pillar size and area of its top drain region also decrease dramatically. This directly results in two significant problems, namely, firstly, the resistance of the drain electrode itself and the contact resistance (Rc) between the drain electrode and the upper contact pad are sharply increased, which severely restricts the read-write speed and energy efficiency of the device, and secondly, the slender column structure is easy to physically bend and even collapse in the subsequent complex manufacturing process (such as deposition, etching, chemical mechanical polishing and the like), so that the device is invalid and becomes a big bottleneck of process integration. To address the problem of pillar bending, the prior art proposes to build a single layer grid support structure similar to a capacitor support structure directly on the pillars. For example, in related patents (e.g., US5874760 a), methods of forming high-density vertical transistor arrays using self-aligned shallow trench isolation techniques are described. Although such designs theoretically achieve a cell area of 4F2, there are inherent drawbacks in directly constructing the grid support on the active pillars, in that firstly, the structure introduces additional parasitic capacitance and may exacerbate the gate leakage current, degrading the electrical performance of the device, secondly, the design of the gate length (Lg) is often limited to accommodate the grid structure, sacrificing the optimization space of the device performance, and thirdly, the "one-cut" support method has limited effect on improving the pillar bending due to stress. In addition, other improvements, such as simply shortening the gate length or developing a novel grid material, can alleviate a certain specific problem to a certain extent, but do not fundamentally solve the core contradiction of mutual correlation and mutual restriction of the three of the increase of drain resistance, the insufficient mechanical stability of the column and the deterioration of parasitic effect. Therefore, an innovative structural design and manufacturing method are urgently needed, and the electrical performance of the drain side is effectively improved and the parasitic effect is reduced while the physical stability of the column is ensured, so that the 4F2 column transistor technology is promoted to be practically applied. Disclosure of Invention The technical problem to be solved by the invention is to overcome the defects in the prior art, thereby providing a semiconductor device and a manufacturing method thereof. In order to achieve the above purpose, the invention adopts the following technical scheme: The present application provides, in a first aspect, a semiconductor device including: A substrate; the active columns are vertically arranged on the substrate, a plurality of active columns are arranged, and each active column comprises a source electrode region, a channel region and a drain electrode region; The gate dielectric layer is formed around the channel region of the active column; the grid electrode is arranged around the grid dielectric layer; A drain extension liner layer formed on sidewalls of the drain region of the active pillars; A grid support structure formed outside the drain extension spacer layer, the grid support structure including a plurality of material layers; a first oxide layer is located between the drain extension liner layer and the grid support structure. In the above scheme, a plurality of vertically arranged active pillars form a basic unit for device integration. By defining the gate dielectric layer around the channel region of the active pillars, the gate dielectric layer does not cover the drain region thereof, thereby providing room for the formation of the drain extension liner layer on the sidewalls of the drain region. The arrangement of the drain extension liner layer directly increases the lateral contact area of the drain, and helps to reduce the resistance when current flows through the drain region. And meanwhile, the grid supporting structure of at least two material layers formed on the outer side of the expansion liner layer provides necessary trans