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CN-121985538-A - RRAM memory device structure and preparation method thereof

CN121985538ACN 121985538 ACN121985538 ACN 121985538ACN-121985538-A

Abstract

The application provides an RRAM memory device structure and a preparation method thereof, wherein a connecting layer is provided, a conductive through hole with preset surface curvature is arranged in the connecting layer, and a memory unit is correspondingly arranged on the conductive through hole, so that the memory unit can be matched with the upper convex surface of the conductive through hole and form a convex area in the forming process. After the programming signal is applied, the electric field correspondingly generated by the RRAM storage device structure is gathered in the inner convex area of the storage unit, and the electric field is led to be gathered towards the curvature center of the convex area, so that the forming probability of a preset interval of the conductive filament in the storage unit is improved, and the purposes of controlling and improving the uniformity and the reliability of the electrical performance of the RRAM device are achieved.

Inventors

  • Pan Xiongbo
  • WANG KUN

Assignees

  • 北京新忆科技有限公司

Dates

Publication Date
20260505
Application Date
20260130

Claims (20)

  1. 1. An RRAM memory device structure, comprising: A connection layer including at least one conductive via; at least one memory cell, set up on said junction layer, and correspond to said conductive through hole one by one; The surface of the conductive through hole, which is close to one side of the storage unit, is configured to be an upper convex surface with a preset curvature, and the storage unit is arranged on the conductive through hole and is matched with the upper convex surface to form a convex area.
  2. 2. The structure of claim 1, wherein the memory cell comprises: a first electrode disposed on the connection layer and covering the upper convex surface corresponding to the conductive via; A resistive layer disposed on the first electrode; the second electrode is arranged on the resistance change layer; Wherein the resistive layer includes a convex portion protruding toward a side close to the first electrode, and a horizontal extension portion circumferentially provided on a peripheral side of the convex portion, the convex portion being located in the convex region.
  3. 3. The structure of claim 2, wherein the memory cell further comprises an oxygen barrier layer and/or an oxygen storage layer, the oxygen barrier layer being disposed on the resistive layer, the oxygen storage layer being disposed on the oxygen barrier layer.
  4. 4. The structure of claim 3, wherein the resistive layer has a thickness in the range of 10 a to 2000 a, the oxygen barrier layer has a thickness in the range of 10 a to 500 a, and the oxygen storage layer has a thickness in the range of 10 a to 2000 a.
  5. 5. The structure according to claim 3, wherein the memory cell includes the oxygen barrier layer and the oxygen storage layer stacked in this order on the resistance change layer, wherein a vertical projection of the oxygen storage layer in a stacking direction of the memory cell is located in a vertical projection plane of the resistance change layer and the oxygen barrier layer, and a projection area is smaller than projection areas of the resistance change layer and the oxygen barrier layer.
  6. 6. The structure of claim 5 wherein said memory cell further comprises a first sidewall spacer disposed on a sidewall surface of said oxygen storage layer and a second sidewall spacer disposed on a sidewall surface of said second electrode, wherein said first sidewall spacer encapsulates a sidewall surface exposed by said oxygen storage layer and said second sidewall spacer encapsulates a sidewall surface exposed by said second electrode.
  7. 7. The structure of claim 6, wherein the first sidewall spacer and the second sidewall spacer have a thickness in the range of 1a to 500 a.
  8. 8. The structure of claim 2, wherein the first electrode comprises at least a first bottom electrode layer and the second electrode comprises at least a first top electrode layer, wherein the thickness of the first bottom electrode layer ranges from 10 a to 1500 a, and the thickness of the first top electrode layer ranges from 10 a to 2000 a.
  9. 9. The structure of claim 8, wherein the first electrode further comprises a second bottom electrode layer having a thickness in a range of 10 a to 200 a.
  10. 10. The structure of claim 8, wherein the second electrode further comprises a second top electrode layer having a thickness in the range of 10 a to 1000 a.
  11. 11. The structure of claim 1, wherein the connection layer comprises a first dielectric layer and at least one first via penetrating through the first dielectric layer, the conductive vias being disposed in the first via in a one-to-one correspondence and filling the first via.
  12. 12. The structure of claim 11, wherein the first dielectric layer has a thickness in the range of 150 a to 2000 a and the upper convex surface has a protrusion height in the range of 10 a to 2000 a relative to the first dielectric layer.
  13. 13. The structure of claim 1, wherein the connection layer is further provided with a first isolation layer, and the first isolation layer wraps a surface exposed on one side of the connection layer, which is close to the memory cell, and extends vertically upwards to wrap a side wall of the memory cell.
  14. 14. The structure according to claim 2, further comprising: the first interconnection comprises a first metal layer arranged on one side close to the storage unit, and one end, far away from the storage unit, of the conductive through hole is arranged on the first metal layer and electrically connects the first electrode with the first interconnection; and the second interconnection comprises a second metal layer arranged on one side close to the memory cell, and the second metal layer is arranged on the second electrode to electrically connect the second electrode with the second interconnection.
  15. 15. The structure of claim 14, wherein the memory cell is further provided with a hard barrier layer, the hard barrier layer is disposed on the second electrode and includes a second via exposing a portion of the second electrode, and the second metal layer is disposed in the second via and contacts the second electrode exposed by the second via to form an electrical connection.
  16. 16. A method for manufacturing an RRAM memory device structure, comprising: Providing a first interconnect; forming a connecting layer on the first interconnection, wherein the connecting layer comprises at least one conductive through hole, and the surface of the conductive through hole far away from one end of the first interconnection is an upper convex surface with a preset curvature; forming a memory stack layer on the connection layer; Patterning and etching the storage stacking layer to form at least one storage unit, wherein each storage unit corresponds to the conductive through hole one by one and is adaptive to the upper convex surface to form a convex area; Forming a first isolation layer on the side wall of the storage unit and the connection layer between the adjacent storage units; forming a first filling layer on the first isolation layer between adjacent memory units; and forming a second interconnection on the storage unit.
  17. 17. The method of claim 16, wherein the step of forming a connection layer over the first interconnect comprises: Forming a first dielectric layer on the first interconnection; etching at least one first through hole on the first dielectric layer, wherein the first through hole exposes part of the first metal layer of the first interconnection; Depositing a metal material in the first through hole, and fully filling the first through hole; And carrying out surface grinding on the metal material deposited and formed in the first through hole to form the conductive through hole with the upper convex surface.
  18. 18. The method of claim 16, wherein the step of forming a memory stack layer over the conductive via comprises: forming a first electrode material layer on the conductive through hole; forming a resistive material layer on the first electrode; and forming a second electrode material layer on the resistance change material layer.
  19. 19. The method of claim 18, further comprising, after the step of forming a layer of resistive material on the first electrode: forming an oxygen-blocking material layer on the resistance-changing material layer, and Forming an oxygen storage material layer on the oxygen barrier material layer; wherein the second electrode material layer is formed on the oxygen storage material layer.
  20. 20. The method of claim 18, further comprising, after the step of forming a second electrode material layer on the resistive material layer: forming a barrier material layer on the second electrode material layer, and Patterning and etching the barrier material layer to form a window exposing part of the second electrode material layer on the barrier material layer; the forming positions of the windows are in one-to-one correspondence with the forming positions of the conductive through holes.

Description

RRAM memory device structure and preparation method thereof Technical Field The application relates to the technical field of semiconductor production processes, in particular to an RRAM storage device structure and a preparation method thereof. Background Resistive random access memory (RESISTIVE RANDOM)An accesssmery, RRAM) device realizes data storage by formation and breakage of conductive filaments in a resistive layer. However, the growth sites of the conductive filaments are random, which also results in unstable device performance. The ideal conductive filament should be formed in an internally homogeneous region within the resistive layer, but in practice the filament is very susceptible to formation in the region of the sidewall where the etching process is susceptible to damage, and the interfacial state of this region is unstable and subject to external environmental disturbances, such that devices based thereon fluctuate significantly in switching parameters, durability and data retention capability. Therefore, how to effectively control the growth position of the conductive filament so as to avoid an unstable edge area, thereby improving the uniformity and reliability of the electrical performance of the RRAM device, and becoming a key technical problem to be solved in the field. Disclosure of Invention The present application aims to solve at least one of the technical problems in the related art to some extent. To achieve the above object, an embodiment of a first aspect of the present application provides an RRAM memory device structure, including: A connection layer including at least one conductive via; at least one memory cell, set up on said junction layer, and correspond to said conductive through hole one by one; The surface of the conductive through hole, which is close to one side of the storage unit, is configured to be an upper convex surface with a preset curvature, and the storage unit is arranged on the conductive through hole and is matched with the upper convex surface to form a convex area. Optionally, the storage unit includes: a first electrode disposed on the connection layer and covering the upper convex surface corresponding to the conductive via; A resistive layer disposed on the first electrode; the second electrode is arranged on the resistance change layer; Wherein, the resistive layer includes protruding portion protruding to the one side that is close to the first electrode, and encircles the horizontal extension portion that sets up in protruding portion week side, protruding portion is located in protruding district. Optionally, the memory unit further comprises an oxygen barrier layer and/or an oxygen storage layer, the oxygen barrier layer is arranged on the resistance change layer, and the oxygen storage layer is arranged on the oxygen barrier layer. Optionally, the thickness range of the resistive layer is 10 a-2000 a, the thickness range of the oxygen barrier layer is 10 a-500 a, and the thickness range of the oxygen storage layer is 10 a-2000 a. Optionally, the storage unit comprises an oxygen barrier layer and an oxygen storage layer which are sequentially stacked on the resistance change layer, wherein the vertical projection of the oxygen storage layer in the stacking direction of the storage unit is positioned in the vertical projection planes of the resistance change layer and the oxygen barrier layer, and the projection area is smaller than the projection areas of the resistance change layer and the oxygen barrier layer. Optionally, the storage unit further comprises a first side wall isolation layer arranged on the side wall surface of the oxygen storage layer and a second side wall isolation layer arranged on the side wall surface of the second electrode, wherein the first side wall isolation layer coats the side wall surface exposed by the oxygen storage layer, and the second side wall isolation layer coats the side wall surface exposed by the second electrode. Optionally, the thickness of the first sidewall isolation layer and the second sidewall isolation layer ranges from 1 a to 500 a. Optionally, the first electrode at least comprises a first bottom electrode layer and the second electrode at least comprises a first top electrode layer, wherein the thickness of the first bottom electrode layer ranges from 10A to 1500A, and the thickness of the first top electrode layer ranges from 10A to 2000A. Optionally, the first electrode further includes a second bottom electrode layer, and the thickness of the second bottom electrode layer ranges from 10 a to 200 a. Optionally, the second electrode further includes a second top electrode layer, and the thickness of the second top electrode layer ranges from 10 a to 1000 a. Optionally, the connection layer includes a first dielectric layer, and at least one first through hole penetrating through the first dielectric layer, where the conductive through holes are disposed in the first through holes in a one