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CN-121985546-A - Low-junction capacitance symmetrical transient voltage suppression diode and preparation method thereof

CN121985546ACN 121985546 ACN121985546 ACN 121985546ACN-121985546-A

Abstract

The invention relates to a low-junction capacitance symmetrical transient voltage suppression diode and a preparation method thereof, wherein the preparation method comprises the steps of silicon wafer cleaning, N-type doping, oxidization, photoetching, deoxidization layer, slotting corrosion, passivation, surface corrosion, electrode manufacturing, metal stripping and cutting; the method comprises the steps of N-type doping, namely carrying out double-sided synchronous diffusion on a silicon wafer by taking POCl 3 as a gas-phase phosphorus source to form a shallow junction N-type region with the junction depth of 1.5-3.0 mu m, carrying out high-temperature oxidation on the silicon wafer with the shallow junction N-type region in an oxygen-containing atmosphere, driving phosphorus atoms to redistribute from the surface to the inside to form a doping profile with the gradient phosphorus concentration from the surface of the silicon wafer, and synchronously growing a surface oxidation layer. The preparation method not only reduces junction capacitance, but also improves symmetry, response speed and pulse tolerance of the bidirectional transient voltage suppression diode by improving doping uniformity.

Inventors

  • ZHANG SHIBO
  • LI XINGLIANG
  • DU JUN
  • Zhao Rongzhuang
  • Ge Dalu
  • TANG FUGUO
  • XIA WEI

Assignees

  • 山东浪潮慧芯微电子科技有限公司

Dates

Publication Date
20260505
Application Date
20260112

Claims (10)

  1. 1. The preparation method of the low-junction capacitance symmetrical transient voltage suppression diode is characterized by comprising the steps of silicon wafer cleaning, N-type doping, oxidization, photoetching, deoxidization layer, slotting corrosion, passivation, surface corrosion, electrode manufacturing, metal stripping and cutting, wherein the N-type doping step is to take POCl 3 as a gas-phase phosphorus source to carry out double-sided synchronous diffusion on the silicon wafer to form a shallow junction N-type region with the junction depth of 1.5-3.0 mu m; The oxidation step is that the silicon wafer forming the shallow junction N-type region is oxidized at high temperature in an oxygen-containing atmosphere, phosphorus atoms are driven to redistribute from the surface to the inside, a doping profile with gradient phosphorus concentration from the surface of the silicon wafer to the inside is formed, and a surface oxidation layer is synchronously grown.
  2. 2. The method for preparing the low-junction capacitance symmetrical transient voltage suppression diode according to claim 1, wherein the N-type doping step is preferably carried out under the condition that nitrogen with the flow of 0.5-1.5L/min carries a gas-phase phosphorus source POCl 3 , and double-sided synchronous diffusion is carried out on a silicon wafer at 1100-1250 ℃ for 1-4 hours to form a shallow junction N-type region with the junction depth of 1.5-3.0 μm.
  3. 3. The method for preparing the low-junction capacitance symmetrical transient voltage suppression diode according to claim 1, wherein the oxidation step is preferably carried out by pushing an N-type doped silicon wafer into an oxidation furnace, introducing dry oxygen with the flow of 1-3L/min at 1100-1200 ℃, keeping the temperature for 0.5-2 hours, driving phosphorus atoms to redistribute into the silicon wafer to form a doping profile with gradually changed concentration from the surface of the silicon wafer to the inside, and synchronously growing a surface oxide layer, and most preferably keeping the temperature for 1 hour.
  4. 4. The method for manufacturing the low-junction capacitance symmetrical transient voltage suppression diode according to claim 1, wherein the electrode manufacturing step is characterized in that an electrode area is defined by photoetching, a Ti/Ni/Ag multilayer metal film is sequentially deposited by a vacuum evaporation method, the thicknesses of a Ti layer, a Ni layer and an Ag layer are respectively 500-1500A, 1500-3000A and 10000-20000A, and finally an electrode is formed by a stripping process, wherein more preferably, the photoetching definition electrode area is selected from 90cp negative photoresist.
  5. 5. The method of manufacturing a low junction capacitance symmetric tvs according to claim 1, comprising one or more of the following conditions: i. The silicon wafer cleaning step comprises the steps of cleaning a silicon wafer by using mixed acid liquid, first liquid and second liquid, flushing the silicon wafer by using water until the water resistance value is larger than 12MΩ & CM, and baking, wherein the further preferred mixed acid liquid comprises nitric acid, glacial acetic acid and hydrofluoric acid with the volume ratio of 15-20:1:1-3, the first liquid comprises ammonia water, hydrogen peroxide and water with the volume ratio of 1:1-3:8-12, the second liquid comprises hydrochloric acid, hydrogen peroxide and water with the volume ratio of 1:1-3:8-12, the most preferred mixed acid liquid comprises nitric acid, glacial acetic acid and hydrofluoric acid with the volume ratio of 18:1:1, the first liquid comprises ammonia water, hydrogen peroxide and water with the volume ratio of 1:2:10, and the second liquid comprises hydrochloric acid, hydrogen peroxide and water with the volume ratio of 1:2:10; the conditions of the photoetching step are that the double sides of the oxidized silicon wafer are subjected to photoresist homogenizing, exposure, development and hardening, wherein, more preferably, the photoetching adopts 450cp negative photoresist; The condition of the oxide layer removing step is that the silicon wafer after photoetching is placed in an oxide layer etching solution, after the oxide layer on the surface is removed, the silicon wafer is cleaned and dried, wherein the oxide layer etching solution further preferably comprises hydrofluoric acid, ammonium fluoride and water in a volume ratio of 1:1.5-2.5:3-3.5, and most preferably the oxide layer etching solution comprises hydrofluoric acid, ammonium fluoride and water in a volume ratio of 1:2:3.3.
  6. 6. The method for manufacturing the low-junction capacitance symmetrical transient voltage suppression diode according to claim 1, wherein the slotting corrosion step is characterized in that a silicon wafer with an oxidation layer removed is placed in a silicon corrosion solution, areas, which are not protected by photoresist, of the upper surface and the lower surface of the silicon wafer are corroded to form grooves for subsequent isolation and device boundary definition, and then cleaning, drying and photoresist removal are sequentially carried out, wherein the silicon corrosion solution further preferably comprises nitric acid, hydrofluoric acid and glacial acetic acid in a volume ratio of 4-6:3-3.5:1, and most preferably comprises nitric acid, hydrofluoric acid and glacial acetic acid in a volume ratio of 5:3.3:1.
  7. 7. The method for manufacturing the low-junction capacitance symmetrical transient voltage suppression diode according to claim 1, wherein the passivation step is characterized in that grooved and corroded silicon wafers are subjected to photoetching and wet etching to deepen or reshape grooves formed on two sides to form isolation grooves, and then the isolation grooves are subjected to glass paste filling and high-temperature sintering processes at least twice to form thick passivation layers covering exposed PN junction side walls so as to achieve good electrical isolation and mechanical protection.
  8. 8. The method for preparing the low-junction capacitance symmetrical transient voltage suppression diode according to claim 1, wherein the surface corrosion step is characterized in that a passivated silicon wafer is subjected to secondary photoetching, then is soaked in hydrofluoric acid solution, a surface oxide layer and mesa glass are removed, the photoresist is removed, then the silicon wafer is put into an oven for drying, further preferably, the secondary photoetching is performed by using 450cp negative photoresist, the hydrofluoric acid solution comprises water and hydrofluoric acid with a volume ratio of 4-6:1, and most preferably, the hydrofluoric acid solution comprises water and hydrofluoric acid with a volume ratio of 5:1.
  9. 9. The method for manufacturing the low-junction capacitance symmetrical type transient voltage suppression diode according to claim 1, wherein the conditions of the metal stripping and cutting steps are that a silicon wafer is soaked in stripping liquid after an electrode is manufactured, surface metal is stripped off by a blue film, then an ultraviolet laser scribing machine is used for cutting according to grooving lines, the front side and the back side of the silicon wafer are cut once by means of a splitting machine, the silicon wafer is split into a single core particle, namely the low-junction capacitance symmetrical type transient voltage suppression diode, the stripping liquid further preferably comprises, by weight, 40% -60% of dimethyl sulfoxide, 20% -30% of monoethanolamine, 10% -20% of deionized water and 0.5% -2% of surfactant, the silicon wafer is soaked in the stripping liquid at 80-90 ℃ for 10-20 minutes, ultrasonic or mechanical oscillation is carried out in the soaking process, the metal pattern is clear, the scribing speed of the ultraviolet laser scribing machine is 200-300mm/s, the power is 2-5W, and most preferably, the stripping liquid comprises, by weight percentage of dimethyl sulfoxide is 50%, 30% of monoethanolamine, and 2% of nonionic surfactant is used for scribing.
  10. 10. A low junction capacitance symmetrical transient voltage suppression diode manufactured by the manufacturing method of the low junction capacitance symmetrical transient voltage suppression diode according to claims 1-9, characterized in that the diode is of a symmetrical N-P-N three-layer structure, wherein the junction depth of an N-type region is 1.5-3.0 μm and has a graded doping profile decreasing from the surface to the internal phosphorus atom concentration, preferably the diode has a junction capacitance of less than 5pF at a bias voltage of 5V, and the deviation of forward and reverse breakdown voltages is not more than 3%.

Description

Low-junction capacitance symmetrical transient voltage suppression diode and preparation method thereof Technical Field The invention relates to a low-junction capacitance symmetrical transient voltage suppression diode and a preparation method thereof, belonging to the field of electronic accessories. Background The bidirectional transient voltage suppression diode is widely applied to overvoltage protection of high-speed circuits such as communication interfaces, data lines and the like. As signal transmission rates continue to increase, more stringent requirements are placed on parasitic parameters of protection devices, and in particular junction capacitance (Cj) needs to be reduced as much as possible to avoid compromising signal integrity. Conventional bi-directional tvs typically employ a phosphor paper solid state diffusion process to form the N-type region. The process has the defects that the phosphorus source concentration is unevenly distributed, the problem of high dispersion of the two-way breakdown voltage (Vbr) of the device is easily caused, the deep junction depth is needed for realizing enough breakdown voltage, the intrinsic junction capacitance of the device is increased, and the lattice defect is easily increased due to long-time diffusion at high temperature, although the cost is lower. Although some of the improved processes employ ion implantation, the equipment costs are high and there is still a junction depth to capacitance contradiction. In addition, the prior art adopts a phosphorus paper diffusion and chemical nickel plating process to form an N-type region, and the technology focuses on solving the problems of voltage consistency and cost, but does not aim at the problem of low capacitance in a high-speed application scene, and the chemical plating process possibly introduces impurities and generates mechanical stress in the electrode forming process, so that the reliability of a shallow junction device is not facilitated. Therefore, development of a symmetrical transient voltage suppression diode capable of remarkably reducing junction capacitance and improving response speed on the premise of ensuring good bidirectional symmetry and reliability and a preparation method thereof are needed. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a low-junction capacitance symmetrical transient voltage suppression diode and a preparation method thereof. The invention mainly solves the technical problems of reducing the junction capacitance of the transient suppression diode, improving the response speed of the transient suppression diode and improving the uniformity of phosphorus source diffusion. The technical scheme of the invention is as follows: The invention provides a preparation method of a low-junction capacitance symmetrical transient voltage suppression diode, which comprises the steps of silicon wafer cleaning, N-type doping, oxidization, photoetching, deoxidization layer, slotting corrosion, passivation, surface corrosion, electrode manufacturing, metal stripping and cutting, wherein the N-type doping step is to take POCl 3 as a gas-phase phosphorus source to carry out double-sided synchronous diffusion on the silicon wafer to form a shallow junction N-type region with the junction depth of 1.5-3.0 mu m; The oxidation step is to oxidize the silicon wafer forming the shallow junction N-type region at high temperature in an oxygen-containing atmosphere, drive phosphorus atoms to redistribute from the surface to the inside, form a doping profile gradually changing from the surface of the silicon wafer to the inside phosphorus concentration, and synchronously grow a surface oxide layer. According to the invention, the N-type doping step is preferably carried out under the condition that nitrogen with the flow of 0.5-1.5L/min is used for carrying a gas-phase phosphorus source POCl 3, double-sided synchronous diffusion is carried out on a silicon wafer for 1-4 hours at 1100-1250 ℃ to form a shallow junction N-type region with the junction depth of 1.5-3.0 mu m, and the junction depth is accurately regulated and controlled by controlling the diffusion time and the temperature. According to the invention, the oxidation step is preferably carried out by pushing the N-type doped silicon wafer into an oxidation furnace, introducing dry oxygen with the flow of 1-3L/min at 1100-1200 ℃, keeping the temperature for 0.5-2 hours, driving phosphorus atoms to redistribute to the inside of the silicon wafer to form a doping profile with gradually changed concentration from the surface of the silicon wafer to the inside, and synchronously growing a surface oxide layer, wherein the most preferably keeping the temperature for 1 hour to realize the optimal doping redistribution effect. According to the invention, the electrode manufacturing step is carried out under the conditions that an electrode area is defined by photoetching, then a Ti/Ni/Ag multilayer