CN-121985547-A - Bidirectional thyristor with composite groove terminal structure and preparation method thereof

CN121985547ACN 121985547 ACN121985547 ACN 121985547ACN-121985547-A

Abstract

The invention relates to the technical field of semiconductor devices and discloses a bidirectional thyristor with a composite groove terminal structure and a preparation method thereof, wherein the bidirectional thyristor comprises an N-type silicon substrate; the semiconductor device comprises two P-type base regions, an N+ type emitter region, a plurality of composite groove terminal structures, a plurality of auxiliary grooves and an oxide layer film, wherein the two P-type base regions are used for forming a plane PN junction in the device together with an N-type silicon substrate, the N+ type emitter region is arranged on one side, far away from the N-type silicon substrate, of the P-type base region, the plurality of composite groove terminal structures are arranged on terminal isolation regions of the N-type silicon substrate, the composite groove terminal structures comprise mesa deep grooves and auxiliary grooves located on the side faces of the mesa deep grooves, the mesa deep grooves are used for achieving physical isolation between an active region and an adjacent device through the groove structures, the auxiliary grooves are used for attracting and redistributing electric field lines when in pressure resistance so as to reduce peak electric fields at the side walls of the mesa deep grooves. The invention can directly and efficiently inhibit peak electric field at the corner of the deep trench of the mesa with extremely low process and area cost.

Inventors

YANG ZHENGFEI
WANG NAN
Peng Xinbao
ZHANG YI

Assignees

江苏捷捷微电子股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260407

Claims (10)

1. A bidirectional thyristor having a composite trench termination structure, comprising: The N-type silicon substrate (1) is provided with terminal isolation areas on both sides of the front surface and both sides of the back surface of the N-type silicon substrate (1); The two P-type base regions (2) are respectively arranged on the front surface and the back surface of the N-type silicon substrate (1), and the P-type base regions (2) are used for forming a plane PN junction in a device together with the N-type silicon substrate (1); The N+ type emitter region (3) is arranged at one side of the P type base region (2) far away from the N-type silicon substrate (1); The N-type silicon substrate comprises a N-type silicon substrate (1), a plurality of composite groove terminal structures, a plurality of semiconductor chip and a plurality of semiconductor chip, wherein the composite groove terminal structures are arranged in terminal isolation areas of the N-type silicon substrate (1), each composite groove terminal structure comprises a mesa deep groove (4) and an auxiliary groove (5) positioned on the side face of each mesa deep groove (4), each mesa deep groove (4) is used for realizing physical isolation between an active area and an adjacent device through the corresponding groove structure, and each auxiliary groove (5) is used for attracting and redistributing electric field lines when in pressure resistance so as to reduce peak electric fields at the side walls of the mesa deep grooves (4); And the oxide layer film (6) is covered on one side of the P-type base region (2) far away from the N-type silicon substrate (1).
2. The triac with a composite trench termination structure of claim 1, further comprising: The SIPOS film (7) is arranged on the inner sides of the mesa deep groove (4) and the auxiliary groove (5) and on one side of the oxide layer film (6), wherein the surfaces of the SIPOS film (7) positioned on the inner sides of the mesa deep groove (4) and the auxiliary groove (5) are sequentially covered with a glass film (8) and an LTO film (9), and the surfaces of the SIPOS film (7) positioned on one side of the oxide layer film (6) are covered with the LTO film (9); The cathode electrode (10) and the gate electrode (11) are positioned on the front side of the N-type silicon substrate (1), and the anode electrode (12) is positioned on the back side of the N-type silicon substrate (1), wherein the cathode electrode (10) and the gate electrode (11) are used for respectively leading out a cathode and realizing gate control, and the anode electrode (12) is used for leading out an anode.
3. The bidirectional thyristor with composite trench termination structure according to claim 1, wherein the auxiliary trench (5) is arranged adjacent to the mesa deep trench (4) in the termination isolation region, and the mesa deep trench (4) has a first trench depth, the auxiliary trench (5) has a second trench depth, the second trench depth being smaller than the first trench depth, and the second trench depth being in the range of one third to two fifths of the first trench depth.
4. A silicon controlled rectifier with a compound trench termination structure according to claim 3, characterized in that the mesa deep trench (4) and the auxiliary trench (5) are both wet chemical etched trench structures comprising sidewalls with an inclined angle and bottom trenches with a radius of curvature; The auxiliary groove (5) is formed through a semiconductor interface formed by a bottom groove with a curvature radius, so that an electric field line originally concentrated at the junction of the side wall of the mesa deep groove (4) and a plane PN junction in the device is offset to the auxiliary groove (5) during voltage resistance, and the local peak electric field at the junction is restrained.
5. A bidirectional thyristor with a composite trench termination structure according to claim 3, wherein the trench depth of the mesa deep trench (4) is 84-90 μm and the trench depth of the auxiliary trench (5) is 31-33 μm for cooperatively improving the forward breakdown voltage and the reverse breakdown voltage of the device.
6. A silicon controlled rectifier with a compound trench termination structure according to claim 2, characterized in that the oxide layer film (6) acts as an electrical insulation layer and passivation layer for reducing the surface state density to stabilize the electrical characteristics of the device and to suppress metal or ion contamination during the fabrication process; the SIPOS film (7) is used as an electric field regulating layer and is used for optimizing the electric field distribution of the terminal surface; the glass film (8) is used as an insulating medium layer and distributed in the mesa deep grooves (4) and the auxiliary grooves (5) and used for blocking ion migration and enabling the surface of the device to be smooth after high-temperature treatment so as to be beneficial to step coverage; the LTO film (9) is used as an outermost protective film and is used for covering and isolating to form a complete surface passivation and protective layer.
7. A method for preparing a bidirectional thyristor with a composite trench termination structure, which is used for preparing the bidirectional thyristor with the composite trench termination structure according to any one of claims 1 to 6, and is characterized in that the preparation method comprises the following steps: providing an N-type silicon substrate (1); P-type impurity ion implantation and diffusion are carried out on the front side and the back side of the N-type silicon substrate (1), and a P-type base region (2) and an oxide layer film (6) are formed on the front side and the back side in a pushing and junction mode in the diffusion process; Forming a first window on the front side and the back side of the N-type silicon substrate (1) through photoetching, removing an oxide layer film (6) in the first window by adopting etching liquid, removing photoresist, cleaning, implanting N-type impurity ions into the first window, and forming an N+ type emitting region (3) and the oxide layer film (6) on the surface through diffusion and push-junction; A second window is formed in the terminal isolation region through photoetching, and wet etching is performed by adopting etching liquid after an oxide layer film (6) in the second window is removed so as to form an auxiliary groove (5); a third window is formed in the terminal isolation region through photoetching, and wet etching is carried out by adopting etching liquid after an oxide layer film (6) in the third window is removed so as to form a mesa deep trench (4), so that a composite trench terminal structure comprising the mesa deep trench (4) and an auxiliary trench (5) is obtained; depositing SIPOS films (7) on the front side and the back side of the N-type silicon substrate (1), and enabling the SIPOS films (7) to enter and cover the mesa deep grooves (4) and the auxiliary grooves (5); preparing glass paste, filling the glass paste into the mesa deep grooves (4) and the auxiliary grooves (5), and sintering to form a glass film (8); depositing LTO films (9) on the front surface and the back surface of the N-type silicon substrate (1) to form an outer protective film; forming a lead window of a cathode electrode (10) and a gate electrode (11) on the front surface of the N-type silicon substrate (1), forming a lead window of an anode electrode (12) on the back surface, and then removing a corresponding film in the lead window; a metal layer is deposited and a cathode electrode (10), a gate electrode (11) and an anode electrode (12) are formed by metal back etching.
8. The method for preparing the bidirectional triode thyristor with the composite groove terminal structure according to claim 7, wherein the P-type impurity ion implantation adopts aluminum ions as implantation ions, the aluminum ions are implanted in a preset implantation energy range and a preset implantation dosage range at an implantation angle vertical to the surface of a silicon wafer, and then a P-type base region (2) is formed through diffusion junction pushing, so that the junction depth of the P-type base region (2) is in a range of 54-58 mu m, and the oxide layer film (6) is simultaneously generated.
9. The method for preparing the bidirectional triode thyristor with the composite groove terminal structure according to claim 7, wherein the N-type impurity ion implantation adopts phosphorus ions as implantation ions, the phosphorus ions are implanted in a preset implantation energy range and a preset implantation dosage range and are diffused and pushed to form an N+ type emitting region (3), the junction depth of the N+ type emitting region (3) is in a range of 10-15 mu m, and the oxide layer film (6) is simultaneously generated.
10. The preparation method according to claim 7, wherein the preparation sequence of forming the auxiliary groove (5) and forming the mesa deep groove (4) is that the auxiliary groove (5) is formed firstly, then the mesa deep groove (4) is formed, the groove depth of the auxiliary groove (5) is in the range of 31-33 μm, and the groove depth of the mesa deep groove (4) is in the range of 84-90 μm so as to form a deep-shallow groove structure; The preparation sequence is used for reducing the influence of photoresist accumulation in the deep trench on development and photoresist removal when photoetching is performed again under the condition that the mesa deep trench (4) is formed, and avoiding the phenomenon that the depth of the trench is converged and the deep and shallow trench structure cannot be formed due to the fact that two trenches are corroded at the same time.

Description

Bidirectional thyristor with composite groove terminal structure and preparation method thereof Technical Field The invention relates to the technical field of semiconductor devices, in particular to a bidirectional thyristor with a composite groove terminal structure and a preparation method thereof. Background In the field of semiconductor devices, bidirectional thyristors are widely used in various power electronic systems such as dimming, speed regulation, temperature control, and the like because of their capability of realizing bidirectional control of an ac circuit. To ensure electrical isolation performance and reliability of the device, it is often necessary to define the active area range using termination isolation structures at the chip edge. In the silicon controlled rectifier product, a mesa deep groove structure is a common scheme for realizing terminal isolation, and a typical double-mesa bidirectional silicon controlled rectifier adopts the structural design. As shown in fig. 3, the deep trench formed by the etching process can effectively isolate different functional regions, but at the same time introduces new technical challenges, especially in terms of the device voltage resistance, there are inherent physical limitations. In the existing mesa silicon controlled device, the side wall of the mesa deep trench formed by an etching process for isolating an active region is necessarily intersected with a planar PN junction in the device body. Since the trench sidewalls formed by etching have geometrically smaller radii of curvature, such junctions result in extremely dense electric field lines when the device is subjected to reverse voltages, resulting in local peak electric field strengths that are much higher than in other regions. The electric field concentration phenomenon caused by the curvature effect causes that avalanche breakdown of the device often firstly occurs at the junction corner of the mesa deep groove and the PN junction, and the actual breakdown voltage is far lower than the theoretical withstand voltage value of the silicon material and lower than the withstand voltage level which can be achieved by the plane junction in the device body. In order to improve the voltage-resistant capability of the mesa silicon controlled rectifier, the technical proposal of optimizing the self shape of the mesa groove or introducing transverse terminal structures such as a field limiting ring is generally adopted in the industry, but the methods have application limitations. For example, by optimizing the sidewall inclination angle and doping profile distribution of the mesa deep trench itself, although the electric field distribution at the corner can be directly improved to a certain extent, the control accuracy requirement of the manufacturing process by this method is extremely high, the process window is very narrow, the actual optimization space is quite limited, and it is difficult to achieve significant performance improvement. For example, the field limiting ring and other transverse terminal structures are adopted, and although the technology is mature, a large amount of chip area is inevitably required, so that the manufacturing cost is greatly increased, and the current development trend of miniaturization and high integration level of the power device is contrary. For another example, a composite terminal structure formed by combining a groove structure and a field limiting ring is selected, the design and the manufacturing process of the structure are too complex, the process steps and the manufacturing difficulty are obviously increased, and a simple scheme for solving the peak electric field problem of the corners of the deep grooves of the mesa is not adopted. Accordingly, there remains a lack of a solution in the art that can directly and efficiently suppress peak electric fields at mesa deep trench corners with minimal process and area costs. For the problems in the related art, no effective solution has been proposed at present. Disclosure of Invention Aiming at the problems in the related art, the invention provides a bidirectional thyristor with a composite groove terminal structure and a preparation method thereof, so as to overcome the technical problems in the prior art. For this purpose, the invention adopts the following specific technical scheme: According to one aspect of the invention, a bidirectional thyristor with a composite groove terminal structure is provided, and comprises an N-type silicon substrate, terminal isolation areas arranged on the front side and the back side of the N-type silicon substrate, two P-type base areas respectively arranged on the front side and the back side of the N-type silicon substrate, a P-type base area used for forming a planar PN junction in a device together with the N-type silicon substrate, an N+ type emitter area arranged on one side of the P-type base area far away from the N-type silicon substrate, a plurality of com