CN-121985548-A - Semiconductor device, method of manufacturing the same, power module, power conversion circuit, and vehicle

CN121985548ACN 121985548 ACN121985548 ACN 121985548ACN-121985548-A

Abstract

The application discloses a semiconductor device, a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the steps of providing a semiconductor body, forming a well region and a first region on the first surface, forming a grid groove on the first surface, performing primary ion implantation on the semiconductor body to form a second region, performing secondary ion implantation on the second region to form a third region, wrapping the bottom of the grid groove, forming the second region on the side, away from the grid groove, of the third region, wherein the conductivity type of the implanted ions of the primary ion implantation is opposite to that of the implanted ions of the secondary ion implantation, and forming a grid in the grid groove. The embodiment of the application can improve the voltage resistance of the trench gate oxide layer, reduce the on-resistance and improve the reliability of the semiconductor device.

Inventors

XIE XIANG

Assignees

安徽长飞先进半导体股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260130

Claims (15)

1. A method of manufacturing a semiconductor device, comprising: The semiconductor body is arranged to be of a first conductivity type and comprises a first surface and a second surface which are oppositely arranged; forming a well region and a first region in the semiconductor body, wherein the first region is of a first conductivity type and is positioned on the first surface, and the well region is of a second conductivity type and is positioned on one side of the first region away from the first surface; Forming a gate trench on the first surface; The bottom of the grid groove is wrapped by the third area, the second area is positioned at one side of the third area far away from the grid groove, and the conductivity type of the implanted ions of the primary ion implantation is opposite to that of the implanted ions of the secondary ion implantation; forming a gate in the gate trench; Forming a source electrode on the first surface; And forming a drain electrode on the second surface.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the performing a first ion implantation on the semiconductor body to form a second region, and then performing a second ion implantation to form a third region, comprises: Performing ion implantation on the grid electrode groove by adopting first conductive ions to form a second area, wherein the second area is positioned at the bottom of the grid electrode groove; Performing secondary ion implantation on the grid electrode groove by adopting second conductive ions to form the third region, wherein the depth of the secondary ion implantation is smaller than that of the primary ion implantation; the forming of the gate trench on the first surface further includes: forming a source electrode groove on the first surface; and when the second region is formed by performing primary ion implantation on the semiconductor body and then the third region is formed by performing secondary ion implantation, the method further comprises the steps of: And implanting ions into the source electrode groove by adopting the conductive ions with the second conductivity type to form a fourth region, wherein the fourth region is positioned at the periphery of the source electrode groove.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the performing ion implantation once to the gate trench using the first conductive ions comprises: Performing ion implantation on the grid groove at a first implantation energy by adopting the first conductive ions with a first ion concentration and a first ion implantation dosage; the second ion implantation of the gate trench by using the second conductive ions comprises: Performing secondary ion implantation on the grid groove at a second implantation energy by adopting the second conductive ions with a second ion concentration and a second ion implantation dosage; wherein the second ion implantation dose is greater than the first ion implantation dose, and the second implantation energy is less than the first implantation energy.
4. The method according to claim 2, wherein the first conductive ions are N-type doped ions, and the second conductive ions are P-type doped ions; Or the first conductive ions are P-type doped ions, and the second conductive ions are N-type doped ions.
5. The method for manufacturing a semiconductor device according to claim 3, wherein, The first ion concentration and the second ion concentration are both greater than ; The first implant energy and the second implant energy are both greater than 1000keV.
6. The method of manufacturing a semiconductor device according to claim 1, wherein forming a gate trench in the first surface comprises: Forming the gate trench and the source trench on the first surface; forming a barrier material layer on the first surface; Removing the barrier material layer positioned on the first surface, the inside of the source electrode groove and the bottom of the gate electrode groove, and forming a barrier layer on the side wall of the gate electrode groove; Before the second ion implantation is performed to form the third region, the method further comprises: and removing the blocking layer positioned on the side wall of the grid groove.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising, before the source is formed on the first surface: Forming an insulating layer on the first surface, wherein the orthographic projection of the insulating layer on the semiconductor body completely covers the orthographic projection of the grid on the semiconductor body; and forming a contact metal layer on the first surface, wherein the contact metal layer covers the insulating layer and the first surface.
8. The method of manufacturing a semiconductor device according to claim 7, wherein forming a source electrode on the first surface comprises: The source electrode is formed on one side of the contact metal layer away from the first surface.
9. A semiconductor device, comprising: The semiconductor comprises a semiconductor body, a well region, a first region, a second region, a first electrode, a second electrode, a first electrode and a second electrode, wherein the semiconductor body is of a first conductivity type and comprises a first surface and a second surface which are oppositely arranged; The bottom of the grid electrode groove is provided with a third area, and one side of the third area far away from the grid electrode groove is provided with a second area; a source electrode positioned on the first surface; and the drain electrode is positioned on the second surface.
10. The semiconductor device of claim 9, wherein a width of the third region is greater than a width of the second region in a direction perpendicular to a thickness of the semiconductor body.
11. The semiconductor device of claim 9, further comprising a source trench and a source trench structure; The source electrode groove is positioned on the first surface, the source electrode groove structure is positioned in the source electrode groove, and the second area is arranged on the periphery of the source electrode groove; The second region has a second conductivity type and the third region has a first conductivity type.
12. The semiconductor device of claim 9, further comprising an insulating layer and a contact metal layer; The insulation layer is positioned on the first surface, and the orthographic projection of the insulation layer on the semiconductor body completely covers the orthographic projection of the grid on the semiconductor body; The contact metal layer is located on the first surface, and the contact metal layer covers the insulating layer and the first surface.
13. A power module comprising a substrate and the semiconductor device of any one of claims 9-12, the substrate being for carrying the semiconductor device.
14. A power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprising a circuit board and at least one semiconductor device according to any one of claims 9-12, the semiconductor device being electrically connected to the circuit board.
15. A vehicle comprising a load and the power conversion circuit according to claim 14, wherein the power conversion circuit is configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.

Description

Semiconductor device, method of manufacturing the same, power module, power conversion circuit, and vehicle Technical Field The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, a power module, a power conversion circuit, and a vehicle. Background The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of the third generation wide bandgap semiconductor such as silicon carbide or gallium nitride has the characteristics of large critical breakdown field strength, high thermal conductivity, large bandgap, high electron saturation drift speed and the like, so that the third generation wide bandgap semiconductor material such as silicon carbide or gallium nitride becomes a research hot spot of a power semiconductor device, and in high-power application occasions such as high-speed railways, hybrid electric vehicles, intelligent high-voltage direct current transmission and the like, the silicon carbide device is endowed with high expectations. However, the trench type MOS device prepared by the prior art has poor voltage resistance and large on-resistance, and affects the reliability and electrical performance of the MOS device. Content of the application The application provides a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle, which are used for improving the voltage resistance of a groove type MOS device, reducing the on-resistance and improving the electrical property and the reliability of the groove type MOS device. In a first aspect, there is provided a method of manufacturing a semiconductor device, comprising: The semiconductor body is arranged to be of a first conductivity type and comprises a first surface and a second surface which are oppositely arranged; forming a well region and a first region in the semiconductor body, wherein the first region is of a first conductivity type and is positioned on the first surface, and the well region is of a second conductivity type and is positioned on one side of the first region away from the first surface; Forming a gate trench on the first surface; The bottom of the grid groove is wrapped by the third area, the second area is positioned at one side of the third area far away from the grid groove, and the conductivity type of the implanted ions of the primary ion implantation is opposite to that of the implanted ions of the secondary ion implantation; forming a gate in the gate trench; Forming a source electrode on the first surface; And forming a drain electrode on the second surface. Optionally, the performing a first ion implantation on the semiconductor body to form a second region, and then performing a second ion implantation on the semiconductor body to form a third region includes: Performing ion implantation on the grid electrode groove by adopting first conductive ions to form a second area, wherein the second area is positioned at the bottom of the grid electrode groove; Performing secondary ion implantation on the grid electrode groove by adopting second conductive ions to form the third region, wherein the depth of the secondary ion implantation is smaller than that of the primary ion implantation; the forming of the gate trench on the first surface further includes: forming a source electrode groove on the first surface; and when the second region is formed by performing primary ion implantation on the semiconductor body and then the third region is formed by performing secondary ion implantation, the method further comprises the steps of: And implanting ions into the source electrode groove by adopting the conductive ions with the second conductivity type to form a fourth region, wherein the fourth region is positioned at the periphery of the source electrode groove. Optionally, the performing ion implantation on the gate trench once by using the first conductive ions includes: Performing ion implantation on the grid groove at a first implantation energy by adopting the first conductive ions with a first ion concentration and a first ion implantation dosage; the second ion implantation of the gate trench by using the second conductive ions comprises: Performing secondary ion implantation on the grid groove at a second implantation energy by adopting the second conductive ions with a second ion concentration and a second ion implantation dosage; wherein the second ion implantation dose is greater than the first ion implantation dose, and the second implantation energy is less than the first implantation energy. Optionally, the first conductive ions are N-type doped ions, and the second conductive ions are P-type doped ions; Or the first conductive ions are P-type doped ions, and the second conductive ions are N-type doped ions. Optionally, the first ion concentration and the second ion concentration are both greater than; The first implant energy and the second impl