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CN-121985551-A - Transistor and preparation method thereof

CN121985551ACN 121985551 ACN121985551 ACN 121985551ACN-121985551-A

Abstract

The disclosure provides a transistor and a preparation method thereof, and belongs to the field of power electronics. The transistor comprises a substrate, a silicon buffer layer and an epitaxial layer, wherein the silicon buffer layer and the epitaxial layer are sequentially laminated on the substrate, and the silicon buffer layer has point defects. The embodiment of the disclosure can improve dislocation defects between the substrate and the epitaxial layer caused by lattice mismatch or thermal mismatch, and improve the reliability of the transistor.

Inventors

  • MA HUAN

Assignees

  • 京东方华灿光电(苏州)有限公司

Dates

Publication Date
20260505
Application Date
20251203

Claims (10)

  1. 1. The transistor is characterized by comprising a substrate (10), a silicon buffer layer (20) and an epitaxial layer (30), wherein the silicon buffer layer (20) and the epitaxial layer (30) are sequentially laminated on the substrate (10), and the silicon buffer layer (20) has point defects.
  2. 2. The transistor according to claim 1, characterized in that the point defect density of the silicon buffer layer (20) is greater than or equal to 1 x 10 16 cm -3 .
  3. 3. A transistor according to claim 1, characterized in that the thickness of the silicon buffer layer (20) is 5nm to 100nm.
  4. 4. A transistor according to any of claims 1 to 3, further comprising a first superlattice buffer layer (40), the first superlattice buffer layer (40) comprising at least one crystal nucleus layer (41), at least one mesh film layer (42) and at least one filling layer (43) alternately stacked in this order, the crystal nucleus layer (41) being for providing crystal nuclei, the mesh film layer (42) being for exposing crystals of the crystal nucleus layer (41) through a mesh, the filling layer (43) being for two-dimensional growth on the mesh film layer (42) to fill up the mesh film layer (42).
  5. 5. The transistor according to claim 4, wherein the nucleation layer (41) comprises an InN layer, the mesh film layer (42) comprises a SiN layer in a mesh shape, and the fill-up layer (43) comprises a GaN layer.
  6. 6. The transistor of claim 4, further comprising a second superlattice buffer layer (50), the second superlattice buffer layer (50) being located between the silicon buffer layer (20) and the first superlattice buffer layer (40), the second superlattice buffer layer (50) being for forming a nucleation layer.
  7. 7. The transistor according to claim 6, wherein the second superlattice buffer layer (50) comprises at least one AlN layer (51) and at least one AlGaN layer (52) alternately stacked.
  8. 8. A transistor according to any of claims 1 to 3, characterized in that the substrate (10) comprises a silicon wafer, a diamond wafer, a gallium nitride wafer, a silicon carbide wafer and a gallium oxide wafer.
  9. 9. A method of manufacturing a transistor, the method comprising: Providing a substrate (10); Forming a silicon buffer layer (20) on the substrate (10), the silicon buffer layer (20) having point defects; an epitaxial layer (30) is formed on the silicon buffer layer (20).
  10. 10. The method of manufacturing according to claim 9, wherein forming a silicon buffer layer (20) on the substrate (10) comprises: And a silicon buffer layer (20) having a growth temperature of 350 ℃ to 600 ℃ and a growth pressure of 50torr to 550torr, and a growth point defect density of 1 x 10 16 cm -3 or more.

Description

Transistor and preparation method thereof Technical Field The present disclosure relates to the field of power electronics, and in particular, to a transistor and a method of making the same. Background A high electron mobility transistor (High Electron Mobility Transistor, HEMT) is a field effect transistor that utilizes two-dimensional electron gas formed at the heterojunction interface as a conductive channel. The transistor has the advantages of high electron mobility, high working frequency, low noise and the like, and is widely applied to various electric appliances. In the related art, a transistor includes a silicon substrate and an epitaxial layer on the silicon substrate. Because of lattice mismatch and thermal mismatch between the silicon substrate and the GaN epitaxial material, high-density threading dislocation and residual stress are easy to generate in the process of growing an epitaxial layer, and the defects can further cause the problems of increased leakage current of a transistor, even early breakdown and the like, so that the epitaxial quality of the transistor is affected. Disclosure of Invention The embodiment of the disclosure provides a transistor and a preparation method thereof, which can improve dislocation defects between a substrate and an epitaxial layer caused by lattice mismatch or thermal mismatch and improve the reliability of the transistor. The technical scheme is as follows: In one aspect, the embodiment of the disclosure provides a transistor, which comprises a substrate, a silicon buffer layer and an epitaxial layer, wherein the silicon buffer layer and the epitaxial layer are sequentially laminated on the substrate, and the silicon buffer layer has point defects. In one implementation of the present disclosure, the point defect density of the silicon buffer layer is greater than or equal to 1×10 16cm-3. In another implementation of the present disclosure, the silicon buffer layer has a thickness of 5nm to 100nm. In another implementation of the present disclosure, the transistor further includes a first superlattice buffer layer including at least one crystal nucleus layer, at least one mesh film layer, and at least one filling layer, which are alternately stacked in order, the crystal nucleus layer is used to provide crystal nuclei, the mesh film layer is used to expose crystals of the crystal nucleus layer through meshes, and the filling layer is used to two-dimensionally grow on the mesh film layer to fill up the mesh film layer. In another implementation of the present disclosure, the nucleation layer comprises an InN layer, the mesh film layer comprises a SiN layer in a mesh shape, and the fill-up layer comprises a GaN layer. In another implementation of the present disclosure, the transistor further includes a second superlattice buffer layer between the silicon buffer layer and the first superlattice buffer layer, the second superlattice buffer layer for forming a nucleation layer. In another implementation of the present disclosure, the second superlattice buffer layer includes at least one AlN layer and at least one AlGaN layer alternately stacked. In another implementation of the present disclosure, the substrate includes a silicon wafer, a diamond wafer, a gallium nitride wafer, a silicon carbide wafer, and a gallium oxide wafer. In another aspect, embodiments of the present disclosure provide a method of manufacturing a transistor, including providing a substrate, forming a silicon buffer layer on the substrate, the silicon buffer layer having a point defect, and forming an epitaxial layer on the silicon buffer layer. Optionally, forming a silicon buffer layer on the substrate includes controlling a growth temperature to be 350 ℃ to 600 ℃, controlling a growth pressure to be 50torr to 550torr, and growing the silicon buffer layer with a point defect density greater than or equal to 1×10 16cm-3. The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least: The transistor provided by the embodiment of the disclosure is formed by introducing a silicon buffer layer with point defects between a substrate and an epitaxial layer. The silicon buffer layer is internally rich in point defects such as vacancies or interstitial atoms. These point defects may diffuse and aggregate under subsequent heat treatment or stress. Point defects generally migrate in order along a specific crystal plane, and when they migrate in order along a specific crystal plane and aggregate to some extent, the regularity of the atomic arrangement in the region is destroyed. The atomic planes originally stacked in a certain order are partially disordered in stacking order due to the aggregation of point defects, so that stacking faults are formed. Stacking faults formed by point defect diffusion in the silicon buffer layer do not occur randomly inside the buffer layer, but occur intensively at the interface of the silicon buffer layer and the e