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CN-121985552-A - Transistor for improving current collapse and preparation method thereof

CN121985552ACN 121985552 ACN121985552 ACN 121985552ACN-121985552-A

Abstract

The disclosure provides a transistor for improving current collapse and a preparation method thereof, and belongs to the field of power electronics. The transistor comprises a substrate, a buffer layer, a leakage blocking layer and a heterojunction, wherein the buffer layer, the leakage blocking layer and the heterojunction are sequentially laminated on the substrate, and the leakage blocking layer comprises a semiconductor layer doped with an iron material. The embodiment of the disclosure can improve the problem that the buffer layer captures electrons to form a virtual grid electrode and prevent the phenomenon of current collapse.

Inventors

  • MA HUAN

Assignees

  • 京东方华灿光电(苏州)有限公司

Dates

Publication Date
20260505
Application Date
20251209

Claims (10)

  1. 1. The transistor is characterized by comprising a substrate (10), a buffer layer (30), a leakage blocking layer (40) and a heterojunction (70), wherein the buffer layer (30), the leakage blocking layer (40) and the heterojunction (70) are sequentially laminated on the substrate (10); The drain blocking layer (40) includes a semiconductor layer doped with an iron-based material.
  2. 2. The transistor according to claim 1, wherein the iron material of the drain blocking layer (40) has a doping concentration of 1 x 10 17 cm -3 to 5 x 10 18 cm -3 , the iron material doped in the drain blocking layer (40) comprising Fe ions and Sc ions.
  3. 3. The transistor according to claim 1, characterized in that the thickness of the drain blocking layer (40) is 450nm to 850nm.
  4. 4. A transistor according to any of claims 1 to 3, characterized in that the drain blocking layer (40) comprises a GaN layer doped with an iron material.
  5. 5. A transistor according to any of claims 1 to 3, characterized in that the transistor further comprises a back barrier layer (60), the back barrier layer (60) being located between the substrate (10) and the heterojunction (70); The back barrier layer (60) comprises a plurality of laminated Al x Ga 1-x N layers, the Al component content of each Al x Ga 1-x N layer increases progressively from the substrate (10) to the heterojunction (70), and the thickness of each Al x Ga 1-x N layer decreases progressively, and x is more than or equal to 0 and less than or equal to 1.
  6. 6. The transistor according to claim 5, characterized in that the thickness of the back barrier layer (60) is 8nm to 50nm.
  7. 7. A transistor according to any of claims 1 to 3, characterized in that the transistor further comprises an electrode layer (90), the electrode layer (90) being located on a side of the heterojunction (70) remote from the substrate (10), the metal layer of the electrode layer (90) adjacent to the heterojunction (70) comprising an iron metal layer.
  8. 8. The transistor according to claim 7, characterized in that the electrode layer (90) comprises a Sc layer, an Al layer and a TiN layer laminated in sequence on the heterojunction (70).
  9. 9. A method of manufacturing a transistor, the method comprising: Providing a substrate; forming a buffer layer on the substrate; forming a leakage blocking layer on the buffer layer, wherein the leakage blocking layer comprises a semiconductor layer doped with an iron material; And forming a heterojunction on the leakage blocking layer.
  10. 10. The method of manufacturing according to claim 9, wherein forming a leak-blocking layer on the buffer layer comprises: And forming a GaN layer doped with an iron material on the buffer layer, wherein the doping concentration of the iron material is controlled to be 1 multiplied by 10 17 cm -3 to 5 multiplied by 10 18 cm -3 , and the iron material comprises Fe ions and Sc ions.

Description

Transistor for improving current collapse and preparation method thereof Technical Field The present disclosure relates to the field of power electronics, and more particularly to a transistor for improving current collapse and a method of manufacturing the same. Background A high electron mobility transistor (High Electron Mobility Transistor, HEMT) is a field effect transistor that utilizes two-dimensional electron gas formed at the heterojunction interface as a conductive channel. The transistor has the advantages of high electron mobility, high working frequency, low noise and the like, and is widely applied to various electric appliances. In the related art, a transistor generally includes a substrate, a buffer layer, and a heterojunction, which are stacked in order. When epitaxially growing on a heterogeneous substrate such as a silicon substrate, a large number of dislocation defects are generated in the buffer layer due to the problem of lattice mismatch between the epitaxial material and the substrate. Under severe working environment with high voltage and high temperature, electrons formed at the heterojunction interface can obtain higher energy and overflow, and are captured by crystal defects of the buffer layer. As the trapped electrons accumulate, a sustained negative charge region is formed in the buffer layer, which is equivalent to creating a virtual gate. The virtual grid electrode can generate a strong depletion effect on the two-dimensional electron gas above, so that a channel is locally narrowed or even interrupted, an expanded depletion region is formed, the channel resistance is increased, the output current is reduced, and a current collapse phenomenon occurs. Disclosure of Invention The embodiment of the disclosure provides a transistor for improving current collapse and a preparation method thereof, which can improve the problem that a buffer layer captures electrons to form a virtual grid and prevent the current collapse phenomenon. The technical scheme is as follows: In one aspect, the embodiment of the disclosure provides a transistor, which comprises a substrate, a buffer layer, a leakage blocking layer and a heterojunction, wherein the buffer layer, the leakage blocking layer and the heterojunction are sequentially laminated on the substrate, and the leakage blocking layer comprises a semiconductor layer doped with an iron material. In one implementation of the disclosure, the iron material of the leakage blocking layer has a doping concentration of 1×10 17cm-3 to 5×10 18cm-3, and the iron material doped in the leakage blocking layer includes Fe ions and Sc ions. In another implementation of the present disclosure, the thickness of the leakage blocking layer is 450nm to 850nm. In another implementation of the present disclosure, the leakage blocking layer includes a GaN layer doped with an iron-based material. In another implementation of the disclosure, the transistor further comprises a back barrier layer, wherein the back barrier layer is located between the substrate and the heterojunction, the back barrier layer comprises a plurality of layers of laminated Al xGa1-x N layers, the Al component content of each Al xGa1-x N layer increases progressively in the direction from the substrate to the heterojunction, and the thickness of each Al xGa1-x N layer decreases progressively, and x is more than or equal to 0 and less than or equal to 1. In another implementation of the present disclosure, the back barrier layer has a thickness of 8nm to 50nm. In another implementation of the present disclosure, the transistor further includes an electrode layer located on a side of the heterojunction remote from the substrate, and the metal layer of the electrode layer proximate to the heterojunction includes an iron metal layer. In another implementation of the present disclosure, the electrode layer includes a Sc layer, an Al layer, and a TiN layer sequentially stacked on the heterojunction. In another aspect, embodiments of the present disclosure provide a method of manufacturing a transistor, including providing a substrate, forming a buffer layer on the substrate, forming a drain blocking layer on the buffer layer, the drain blocking layer including a semiconductor layer doped with an iron-based material, and forming a heterojunction on the drain blocking layer. Optionally, forming a leakage blocking layer on the buffer layer includes forming a GaN layer doped with an iron material on the buffer layer, the iron material being controlled to have a doping concentration of 1×10 17cm-3 to 5×10 18cm-3, the iron material including Fe ions and Sc ions. The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least: The leakage blocking layer in the transistor provided by the embodiment of the disclosure can effectively inhibit leakage by doping the iron material. The ferrous material has spontaneous polarization characteristic, and the polarizatio